臺灣博碩士論文加值系統

隨著半導體製程技術的演進，製程變動(process variation)所造成元件之間的不匹配(mismatch)與導線寄生效應(parasitic effect)的相對變異也越來越嚴重，這也導致了設計上的高複雜度及高時間成本，因此，佈局自動化也就成為類比電路設計的一個重要角色。

在類比電路上為了降低設計時的高錯誤率、高複雜度的佈局操作所花費的時間與繁瑣的任務和昂貴的設計成本，所以佈局的自動化設計將成為類比設計過程中一個關鍵的角色。由於敏感的寄生電容效應、元件的不匹配、製程變動與梯度效應都將導致佈局結果可能是一個不好的佈局，也造成了產品的不準確性與良率的降低。多數類比電路像是類比數位/數位類比轉換器或濾波器等等，其性能都依賴於準確的電容比值。對於要求準確的電容比值大都會使用多顆單位電容並聯取代單一顆大電容並考慮繞線引起的寄生效應，以減少一些不匹配的影響。

本論文提出一種整合電容陣列區塊產生器，我們提出一種App的系統，讓使用者可以快速產生電容陣列，依序透過四個步驟:初始參數設定、電容擺放、繞線設定及寄生電容的萃取，便可產生電容陣列區塊，對於包含多個特定電容的陣列以此方法也能完成。。在後面的章節會舉出各種不同的特定電容比值之電容陣
列的例子，第一組數據是開關式電容電路電容比值為1:1 電容陣列，第二組數據是雙二階開關式電容電路連續電容比值電容陣列，最後一組則提出連續漸進暫存器類比數位轉換器連續電容指數比值電容陣列。在整個佈局完成後，最後會透過Calibre來萃取繞線產生的寄生電容，並計算其電容比值，以及測量繞線加上單位電容的面積，來讓使用者去評估是否符合自己所需要的電容。

As the device shrinking of semiconductor process, the process variation causes the mismatch and wire parasitic effect between elements becomes much more seriously. It also causes high complexity and time-consuming on design circuits. Therefore, layout automation is likely to play a key role in analog circuit design.

The performance of many types of analog circuits, like ADC, DAC, or filters etc., relies on the implementation of accurate capacitor ratio. Besides the elements matching, the circuit yield also suffers from the effect of parasitic capacitances. By considering the parasitic effect between each unit capacitor, several smaller unit capacitors will be parallel connected to replace the whole bigger capacitor to reduce these mismatch effects. In this thesis, a yield-aware capacitor array block creator, called App_CABC, is proposed to generate a capacitor array block. User can produce capacitor array fast and good. By a four-step procedure including initial parameter setting, capacitor placement, capacitor routing, parasitic capacitor and extraction, the capacitor array block will be produced. The router can be not only applied to the case of a pair of two targets but also to the multiple target capacitors. By the conjunction of an array assignment using of spatial correlation feature, three cases are used as examples to demonstrate the assignment-routing flow. The first is a case of two targets with a ratio of 1:1. The second is a case of multiple targets with continuous ratio of 45:16:2:1. The last is a case with exponentially continuous ratio of 8:4:2:1:1. After finishing layout creation, the wire parasitic capacitor will be extracted from Calibre. Finally, the accuracy of capacitor ratio and layout area will be contrasted for the evaluation the satisfaction.

摘 要 i
Abstract ii
致謝 iii
Table of Contents iv
List of Figures vi
List of Tables vii
Chapter 1. Introduction 1
Chapter 2. Capacitor Array Block 3
2.1 Capacitor Introduction 3
2.2 Capacitor Mismatch 5
2.3 Enhancement of Capacitor Match 7
2.4 Spatial Correlation 9
2.5 Elements of Correlation & Ratio Variance 15
Chapter 3. App-CABC 19
3.1 Graphical User Interface 19
3.1.1 Graphical User Interface Design Rule 19
3.1.2 Graphical User Interface 21
3.2 App-CABC Function & Performance 21
3.2.1 Initialization List 21
3.2.2 Initialization Setting 22
3.3 App-CABC 23
Chapter 4.Experiment & Analysis 28
4.1 Application to Benchmark Circuits 28
4.1.1 Switched Capacitor Circuit 29
4.1.2 Fleischer-Laker Switched Capacitor Biquad Circuit 31
4.1.3 Successive Approximation Register Analog-to-Digital Converter 33
4.2 Application to interface and platform 35
Chapter 5. Conclusions 39
References 40

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