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研究生:周芳嬪
研究生(外文):Fang-ping Chou
論文名稱:高速 850-nm 矽光檢測器設計與分析
論文名稱(外文):Design and Analysis of 850 nm Si Photodiodes in Standard CMOS Technology
指導教授:辛裕明
指導教授(外文):Yue-ming Hsin
學位類別:博士
校院名稱:國立中央大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:91
中文關鍵詞:光檢測器標準製程
外文關鍵詞:PhotodiodesCMOS850 nm
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本論文所討論的光通訊元件為利用較便宜的矽(Silicon)材料並結合商用標準
CMOS 製程製作的矽光檢測器(Si photodetector),利用此方式製作的元件俱有大幅降
低成本及容易與後端電路整合製成光電積體電路(OEIC)的特性。
使用 商用 CMOS 製程來實現 850-nm 光檢測器最關鍵的問題其一便是速度,由於
商用 CMOS 製程屬於平坦化且表面的製程,實際可應用的 n/p 層(layer)最深也只在 2
~ 3 µm 之間。對入射光波長為 850 nm 的光訊號而言,矽材料的吸收深度(absorption
depth)約為 20-µm,此意味著大部分的光會落在表面元件之外的基板中,無法直接被
表層形成的元件空乏區內之電場收集到。這些在基板中吸光而產生的電子電洞對,會
先以擴散運動方式慢速的到達空乏區而被電極收集,因而大幅地影響了光檢測器的操
作速度。加上標準 CMOS 製程無法更動製程條件,元件的設計與特性改善只能利用
現有層數和佈局來改善。研究上首先利用基本 pn 二極體結構的光檢測器(PD)來比較
三種不同形狀佈局光檢測器的表現,包括傳統長條型、環繞式四邊形、與環繞式八邊
型,量測結果顯示,環繞式八邊型的結構有對稱電場分佈能達到較佳的頻寬、響應度
表現,因此本論文的後續正面照光光檢測器都採用八邊型的佈局。
為了改善光檢測器的速度特性,提出了三種方法來達到高速的目標。第一種方法
是利用 pwell 包圍在元件最外圍形成一圈 body 的結構,接下來給予 body 電極適當的
偏壓,讓其與光檢測器內部接地的 p 端形成電流路徑。當基板因照光產生慢速載子而
往元件主動區移動時,慢速載子會被此電流路徑帶走而不影響元件本身,進而提高元
件的頻寬。並且透過適當的 body 偏壓與 PD 元件偏壓配合,能讓元件操作在低偏壓
3-V 達到頻寬 2.46GHz,符合實際的低壓操作運用。第二個方法是利用側面照光的方
式,將光藉由側面照射至元件表面,避免入射光照射到基板,減少基板產生慢速載子
的困擾。但標準製程實現測照 PD 的困難在於如何定義受光面,本論文利用 CIC 提供
的後製程(MEMS)蝕刻出受光面,再用切割的方式露出受光面以利光纖照光。基本 pn
結構為長條型,光檢測器頻寬由正面入射照的 1.4 GHz 提升至側面入射照的 2.6GHz。
第三種方法是利用 0.18 µm CMOS 製程裡的較深層 deep n-well 來阻擋基板的慢速載
子,若要確實達到阻隔慢速載子必須要在 deep n-well 增加額外的電極來將電子帶走
加上,並利用基板接地帶走慢速電洞共同達成。此方法的光檢測器頻寬可大幅提升至
8.7 GHz,為目前文獻上利用商用 CMOS 製程實現的最快速 850-nm 矽光檢測器。除了利用頻寬來確認基板慢速載子的排除效果,另外也藉由多餘噪音雜訊(excess noise)
的量測結果來佐證,比較三種研究方法的元件之多餘噪音雜訊量測結果,矽光檢測器
具有 deep n-well 另給偏壓的方式可以得到最低雜訊指數(noise factor) 5.3。
This dissertation proposes the photodetectors using cheaper silicon material combined
with standard CMOS technology without any process modifications. To enable the
cost-effective implementation of the optical short-distance interconnection, Si CMOS
technologies is a good, low-cost approach for general 850 nm transmitter and provide a
universal platform for the monolithic integration of available, complex, and high-speed
circuits with Si photodetectors to form an all-Si optical receiver (OEIC).
One of the most crucial issues for 850 nm Si photodiodes in standard CMOS technology
is the response speed. Because the penetration depth (∼ 20 μm) of the 850 nm-wavelength
light into Si is much deeper than that of the depth of the depletion (∼ 2 μm) in the surface
p-n diodes. As a result, a large portion of carriers is generated in the Si substrate and
diffuse in all directions. The slow diffusion carriers will reach the depletion region and led
to the slow response of the p-n PD.
Researchers have studied several device layouts to optimize device performance. Silicon
photodiodes (PDs) with different layouts in standard 0.18-μm CMOS technology are
systematically presented and discussed first in this dissertation. Different layout geometries
of PDs are realized including conventional rectangle, square and octagon layouts. A basic
p-n PD with octagon layout demonstrates higher responsivity and lower capacitance with
improved bandwidth. Therefore, the vertically illuminated PDs with octagonal layout are
used in this dissertation.
To improve the speed characteristics of the photodetector, three methods are proposed to
improve the bandwidth. First, a basic p-n PD with body contact presents a method to
eliminate the slow photocarriers by adopting a body contact design to create a current flow
under the PD to remove the slow diffusion carriers.. With the appropriate bias between PD
and body contact, a low bias and high-speed PD can be achieved for practical applications.
The 3dB bandwidth of PD is 2.46 GHz at low bias 3 V.
Secondly, the edge-illuminated Si PDs with standard CMOS technology by employing
an MEMS process to expose the coupling edge surface is realized. A single-mode lensed
fiber is employed to inject light into the depletion region of the PD, thereby limiting and
reducing the diffusive carriers within the bulk Si substrate. Consequently, the
edge-illuminated PD with conventional rectangle layout shows the improved 3-dB
bandwidth from 1.4 GHz to 2.6 GHz in comparison to the vertically illuminated Si PDs.
The third method is that using deep n-well implantation in standard CMOS technology
to block the slow diffusion carriers from substrate. Two different bias schemes (normal
bias and extra bias) on the deep n-well are used to analyze the effects of deep n-well bias on the bandwidth and gain-bandwidth performances of Si PDs. The extra bias in the PD
not only blocks the hole and collects electrons from the substrate, but also improves the PD
performance. This design achieves the highest bandwidth (8.7 GHz) and a large
gain-bandwidth product of 542 GHz with a reverse bias of 11.45 V and an extra voltage of
11.45 V but low-magnitude of output signal in standard CMOS technology. This is the
highest bandwidth reported for silicon photodetectors fabricated using standard CMOS
technology and the highest gain-bandwidth product in 0.18 µm CMOS technology. In
addition to bandwidth, excess noise measurement is a way to confirm the effect of
excluding substrate carrier. Si PDs in this dissertation with extra bias in the deep n-well
demonstrates the lowest noise figure (noise factor) of 5.3 due to the removal of slow
diffusion carriers.
Abstract III
Acknowledgement V
Contents VI
List of Tables IX
List of Figures X
Chapter 1
Introduction 1
1.1 Motivation 1
1.2 Organization of this Dissertation 8
Chapter 2
Body Bias Technique for Low-voltage Operation 10
2.1 Introduction 10
2.2 Symmetric Layout 11
2.2.1 Device Structures 11
2.2.2 Devices Performance 13
2.3 Body Bias Technique 16
2.3.1 Device Structures 16
2.3.2 Body Bias Technique and Simulation 18
2.3.3 Devices Performance 23
2.3.3.1 DC Performance 23
2.3.3.2 AC Performance 27
2.3.3.3 Excess noise performance 31
2.4 Summary 33
Chapter 3
Edge-illuminated Si Photodiodes 34
3.1 Introduction 34
3.2 Design Description 34
3.3 Devices Performance 39
3.3.1 DC Performance 39
3.3.2 AC Performance 42
3.3.3 Excess noise performance 44
3.4 Summary. 45
Chapter 4
Effect of Deep N-Well Bias 46
4.1 Introduction 46
4.2 Device Structure 46
4.3 Bias Schemes and Simulation 49
4.4 Devices Performance 52
4.4.1 DC Performance 52
4.4.2 AC Performance 55
4.4.3 Excess noise performance 58
4.5 Summary 59
Chapter 5
Conclusion and Future Work 60
5.1 Conclusion 60
5.2 Future Work 62
5.2.1 Ge film on CMOS PD 62
5.2.2 CMOS PD with deep substrate contact 64
5.2.3 CMOS PD with substrate removing 65
References 68
Publication List 73
Journal Papers List 73
Conference Papers 73
Patents and Honor 74

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