(34.204.201.220) 您好!臺灣時間:2021/04/20 12:27
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:張家豪
研究生(外文):ZHANG,JIA-HAO
論文名稱:利用三維矽波導光路實現10-Gbps單晶片光學連接模組
論文名稱(外文):On-Chip 10-Gbps Optical Interconnect Module Using Three-Dimensional Silicon Optical Waveguides
指導教授:伍茂仁
指導教授(外文):Mao-Jen Wu
學位類別:碩士
校院名稱:國立中央大學
系所名稱:光電科學與工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:69
中文關鍵詞:光連接模組單晶片波導
外文關鍵詞:optical interconnect moduleon chipwaveguides
相關次數:
  • 被引用被引用:0
  • 點閱點閱:250
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在目前多核心架構下,核心與核心之間的連接需要高傳輸量的介面,而晶片上之光連接模組是能夠提供大資料傳輸的解決方法,於是在本研究中提出利用三維矽波導光路實現10-Gbps單晶片光學連接模組。此模組整合了主動元件雷射、光偵測器、驅動電路晶片以及矽波導於一個矽基板上,使用者只需要調制驅動電路晶片而不需要考慮光電介面轉換的問題。
在本論文中訊號的傳遞路徑依序是:驅動端積體電路晶片、面射型雷射、45°微反射面、矽波導、45°微反射面、光偵測器、接收端放大器電路晶片,此訊號由雷射出發之後,經由45°微反射面達到光路垂直轉折之目的,耦合進入矽波導中,再經由另一個45°微反射面垂直轉折進入光偵測器,實現三維光路之架構。本光學連接模組使用SOI晶圓當作基板,在光子元件層使用非等向性濕蝕刻製程一次步驟製作出光波導以及45°微反射面,接著在絕緣層上建構高頻傳輸線以及封裝上主動元件,最後利用打線的方式整合積體電路晶片於發射與接收端。
本光學連接模組之光學損耗經過量測可達2.22 dB,在高頻的量測初使條件:雷射由驅動電路供給電流10 mA、出光功率是1.82 mW、調制電流12.5 mA,放大器電路供給光偵測器1.7 V負偏壓,偽隨機二進位序列為2-31-1;量測到眼圖之眼高可達218 mV、訊雜比24、抖動為30.22 ps、誤碼率可以通過10-12等級。由此可證明本模組具有傳輸10-Gbps資料量的能力

Due to the new semiconductor technologies such as multi-core processors are more popular, the interface to transmitting high data rate of core-to-core interconnect is important. On-chip interconnect module is the solution to overcome the high data rate demand in next generation. Here, we demonstrate an on-chip 10-Gbps optical interconnect module using three-dimensional silicon optical waveguides. This optical module include the vertical-cavity surface-emitting laser (VESEL), driver IC, amplifier IC, photodiode (PD), all integrated in the one silicon substrate. The system is optically complete and closed without any optical inputs or outputs, users do not have to worry about any optical issues, could only control the driver IC to operate the system.
In this thesis, we use the 45° micro-reflector to achieve three-dimensional optical path. Signal transmission path is showed below, controlling driver IC to generate electric signal for VESEL, VESEL convert signal from electrical to optical, and the laser beam emitting from the VCSEL array is coupled into the waveguide via a 45° micro-reflector, propagates along the waveguide, and then is coupled into the PD via another 45° micro-reflector, finally the signal converted from optical to electrical and arrived to the amplifier. Proposed on-chip 10-Gbps optical interconnect module is based on SOI wafer. The 45° slants and proposed waveguide are fabricated on the device layer of (100)-oriented SOI wafer using anisotropic wet etching. The VESEL, PD, driver IC, amplifier are assembled on the isolation layer and connect the PCB by wire bonding.
According to the optical simulated and experiment results, optical loss achieve 2.22 dB. Initial condition for high-frequency measurement : Driver IC supply 10 mA driver current to VCSEL, modulation current is 12.5 mA, output power is 1.82 mW. Amplifier supply -1.7 voltage to PD. Delivering a 2-31-1 PRBS signal at 10-Gbps at wavelength of 1310 nm. Finally we get a eye diagram for the data rate at 10-Gbps. The eye height is 218 mV, signal to noise Ratio (SNR) is 24, jitter is 30.22 ps, the eye is wide open with a BER < 10-12, indicating a good transmission capability.

0目錄
摘要 I
ABSTRACT III
目錄 V
圖目錄 VIII
表目錄 XI
第一章 緒論 1
1-1 研究動機 1
1-2 晶片上光連接模組之發展狀況 3
1-3 本研究提出利用三維矽波導光路實現10-GBPS單晶片光學連接模組 9
第二章 具三維矽波導光路10-GBPS單晶片光學連接模組設計 11
2-1 以矽波導實現三維光路之模組設計 13
2-1-1具三維矽波導光路之單晶片光學連接模組膜層間之菲涅耳損失分析與設計 15
2-1-2 矽基板厚度與光場擴張效應分析 16
2-1-3 矽波導之尺寸架構與主動元件匹配分析 17
2-2具三維矽波導光路之單晶片光學連接模組光學特性模擬 19
2-2-1 光波導結構設計 19
2-2-2 單晶片光學連接模組光學效率模擬及波導尺寸設計 19
2-3 主動元件之光電特性 25
2-3-1 面射型雷射之架構規格以及光電特性的量測 25
2-3-2光檢測器之架構規格以及光電特性的量測 27
2-4 具三維矽波導光路之單晶片光學連接模組高頻傳輸線設計 30
2-4-1 光學連接模組高頻傳輸線模型設計方法 30
2-4-2 光學連接模組高頻傳輸線之結構尺寸 31
2-4-3具三維矽波導光路之單晶片光學連接模組高頻傳輸線模擬結果 34
第三章 具三維光路單晶片光連接模組製程開發 37
3-1具三維矽波導光路之單晶片光學連接模組梯形矽波導的製程開發 38
3-2具三維矽波導光路之單晶片光學連接模組化學機械研磨製程開發 42
3-3 高頻傳輸線以及金屬焊料之金屬製程開發 44
3-4 封裝製程開發 47
第四章 具三維矽波導光路10-GBPS單晶片光連接模組高頻特性量測 50
4-1 高頻傳輸線之散射參數量測結果 50
4-2 具三維矽波導光路10-GBPS單晶片光連接收發模組之高頻特性量測 53
4-2-1 主動元件封裝後之光電特性以及光學耦和效率 53
4-2-2 光連接模組頻率響應 56
4-2-3 光連接模組之眼圖量測 60
4-2-4 光連接模組眼圖與誤碼率之關係探討 64
第五章 結論 69

[1] J. A. Davis, R Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahamn, R. Reif, and J. D. Meindl, “Interconnect Limits on Gigascal Intergration (GSI) in the 21st Century” Proc. IEEE Micro, vol. 89, pp. 305-324, (2001).
[2] David A. B. Miller and H. M. Ozaktas, “Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture” J. Parallel Distrib. Comput., vol. 41, p. 4252, 1997.
[3] K. C. Sarawat and F. Mohammadi, “Effect of Scaling of Interconnections on the Time Delay of VLSI Circuit” IEEE Trans. Electron Devices, vol. ED-29, no. 4,pp. 645-650 (1982).
[4] David M. Pozer “Microwave Engineering” John Wiley & Sons, Inc. 2005.
[5] David A. B. Miller “Physical Reasons for Optical Interconnection,” Int. J. Optoelectronics 11,155-168 (1997).
[6] David A. B. Miller “Device Requirement for Optical Interconnects to Silicon Chips” IEEE (2009).
[7] Yasuhiko Arakawa and Takahiro Nakamura “Silicon Photonics for Next Generation System Integration Platform” Communications Magazine, IEEE, vol. 51, p. 72-77, 2013.
[8] Shimizu, T. ; Okano, Makoto ; Hatori, N. ; Ishizaka, M. ; Yamamoto, Tsuyoshi ; Baba, T. ; Akagawa, T. ; Akiyama, S. ; Usuki, T. ; Okamoto, D. ; Miura, M. ; Noguchi, M. ; Fujikata, J. ; Shimura, D. ; Okayama, H. ; Tsuchizawa, T. ; Watanabe, Toshifumi ; Yamada, K. ; Itabashi, Seiichi ; Saito, E. ; Nakamura, T. ; Arakawa, Yasuhiko ‘First demonstration of high density optical interconnects integrated with lasers, optical modulators and photodetectors on a single silicon substrate” Optical Communication (ECOC), 2011
[9] B. Ciftcioglu, R. Berman, S. Wang, J. Hu, I. Savids, M. Jain, D. Moore, M. Huang, E. g. Friedman, G. Wicks and H. Wu, “3-D Integrated Heterogeneous Intra-Chip Free-Space Optical Interconnect” Optical Interconnects Conference, IEEE, p. 56-57, 2012.
[10] K. Preston, L Chen, S Manipartruni, and M. Lipson “Silicon photonic interconnect with micrometer-scale devices” Group IV Photonics, 2009. IEEE International Conference.
[11] V. R. Shrestha, H-S Lee, W-J Kim, and S-S Lee “High speed optical interconnect based on grating coupler assisted silicon nitride waveguides” OECC, 2012 17th, p. 643-644.
[12] J. V. Campenhout, P. R. A. Binetti, P. R. Romeo, P. Regreny, C. Seassal, X. J. M. Leijtens, T. de Vries, Y. S. Oei, R. P. J. van Veldhoven, R. Nötzel, L. Di Cioccio, J. M. Fedeli, M. K. Smit, D. Van Thourhout, and R. Baets, “Low-Footprint Optical Interconnect on an SOI Chip Through Heterogeneous Integration of InP-Based Microdisk Lasers and Microdetectors,” IEEE Photon. Technol. Lett. 21(8), 522-524 (2009).
[13] D. Vermeulen , S. Selvaraja , P. Verheyen , G. Lepage , W. Bogaerts , P. Absil , D. Van Thourhout and G. Roelkens, “High-Efficiency Fiber-to-Chip Grating Couplers realized using An Advanced CMOS-Compatible Silicon-On-Insulator Platform” 2010 Optical Society of America.
[14] B. E. Lemoff, M. E. Ali, G. Panotopoulos, G. M. Flower, B. Mahdavan, A. F. J.Levi, and D. W. Dolfi, “MAUI: Enabling fiber-to-processor with parallel multiwavelength optical interconnects,” IEEE J. Lightwave Technol., 22, 2043-2054 (2004).
[15] F. Wang, F. Liu, and A. Adibi, “45 degree polymer micromirror integration for board-level three-dimensional optical interconnects,” Opt. Express, 17, 10514-10521 (2009)

連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔