[1] D. A. B. Miller, "Device requirement for optical interconnects to silicon chips," Proc. IEEE Special issue on silicon photonics, 2009
[2] S. Hiramatsu and T. Mikawa, “Optical design of active interposer for high-speed chip level optical interconnects,” IEEE J. Sel. Top. Quantum Electron., 24(2), 927-934 (2006).
[3] M. Aljada, K. E. Alameh, Y. T. Lee, and I. S. Chung, “High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors,” Opt. Express, 14(15), 6823-6836 (2006).
[4] X. Wang and R. T. Chen, “Fully embedded board level optical interconnects — From point-to-point interconnection to optical bus architecture,” Proc. SPIE, 6899, 6899031-6899039 (2008).
[5] A. F. J. Levi, “Optical interconnects in systems,” Proc. IEEE, vol. 88,no. 6, pp. 750–757, Jun. 2000.
[6] A. F. Benner et al., “Exploitation of optical interconnects in futureserver architectures,” IBM J. Res. Develop., vol. 49, no. 5, pp. 759–782,2005.
[7] A. F. Benner, P. K. Pepeljugoski, and R. J. Recio, “A roadmap to 100G Ethernet at the enterprise data center,” IEEE Trans. Commun. Mag., 45(11), pp. 10–17, Nov. 2007.
[8] P. Kapur, J. P. Mc Vittie, and K. C. Saraswat, “Technology and reliability constrained future copper interconnects. I. Resistance modeling,” IEEE Trans. Electron Devices, 49(4), pp. 590-597, Apr. 2002.
[9] P. Kapur, G. Chandra, J. P. Mc Vittie, and K. C. Saraswat, “Technology and reliability constrained future copper interconnects. II. Performance implications,” IEEE Trans. Electron Devices, 49(4), pp. 598-604, Apr. 2002.
[10]A. Shacham, K. Bergman, and L. P. Carloni, BOn the design of a photonic network-on-chip, presented at the Int. Symp. etworks-on-Chips, Princeton, NJ,May 2007, paper 2.1.
[11] Aleksandr Biberman, Keren Bergman, “Optical interconnection networks forhigh-performance computing systems,” Rep. Prog. Phys. January, 2012, 046402 (15pp)
[12] Wei-Chao Chiu, Cheng-Yen Lu, and Ming-Chang M. Lee, “Monolithic Integration of 2-D Multimode Interference Couplers and Silicon Photonic Wires,” IEEE J SEL TOP QUANT, 17(3), pp. 540–545,MAY/JUNE 2011
[13] Hidetoshi Numata, Shigeru Nakagawa, Yoichi Taira, Shimotsuruma, Yamato, “Three-Dimensional Low-loss Waveguide Shuffler and Splitter Combiner using Novel Mirror Structure,” ECOC, September, 2009
[14]Woo-Jin Lee, Sung Hwan Hwang, Myoung Jin Kim, Eun Joo Jung, Jong Bea An,Gye Won Kim, Myung Yung Jeong, and Byung Sup Rho,” Multilayered 3-D Optical Circuit With Mirror-Embedded Waveguide Films,” IEEE Photon Tech Lett, 24(14), pp. 1179-1181, JULY 15, 2012
[15]Y. Urino et.al.“First demonstration of high density optical interconnects integrated with lasers, optical modulators, and photodetectors on single silicon substrate,” Opt. Express, vol. 19, pp. B159 – B165, Nov. 2011.
[16] David M. Pozer “Microwave Engineering” John Wiley & Sons, Inc. 2005
[17] 許志宏,”具繞射式光學元件之矽基45微反射面研究,” (中央大學光電所碩士論文, 台灣, 2007)[18] B. E. Lemoff, M. E. Ali, G. Panotopoulos, G. M. Flower, B. Mahdavan, A. F. J.Levi, and D. W. Dolfi, “MAUI: Enabling fiber-to-processor with parallel multiwavelength optical interconnects,” IEEE J. Lightwave Technol., 22, 2043-2054 (2004).
[19] F. Wang, F. Liu, and A. Adibi, “45 degree polymer micromirror integration for board-level three-dimensional optical interconnects,” Opt. Express, 17, 10514-10521 (2009).
[20] Kun-Mo Chu, Jung-Sub Lee, Han Seo Cho*, Hyo-Hoon Park*, and Duk Young Jeon, “A Fluxless Flip Chip Bonding for VCSEL Arrays Using Silver Coated Indium Solder Bumps,” IEEE Conference,2004