臺灣博碩士論文加值系統

隨著人類的需求，電子產品不斷朝著輕薄短小的方向邁進，不僅要求小小設備可容納豐富的功能，也要省電。因此積體電路(integrated circuit)製程技術也不斷進步，促使單位晶片面積當中的電晶體數量大幅提升、工作電壓下降。但是採用先進的半導體技術會有製程變異及設備老化的問題，進而造成電路發生時序錯誤(timing error) 。而時序錯誤會對效能產生極大的影響，所以保持電路的可靠度成為一項非常重要的議題。
本論文將提出一種容忍多重時序錯誤之可重組數位濾波器設計，其擁有錯誤偵測(error detection)及錯誤容忍(error tolerance)之功能，使電路即使發生時序錯誤亦可持續正常運作並產生正確的輸出。雖然犧牲了少量的面積成本及功率消耗，卻可換取電路的可靠性，進而提升效能。文中也將此種容錯設計應用在各種數位訊號處理電路(Digital Signal Processing)，並針對不同的路徑提出相對應的解決方式。
最後，將範例FIR及IIR電路的原始電路和增加了容錯設計之電路兩者之面積、速度、功率消耗予以分析比較，並在文末做出總結。

As the feature size of chips shrinks with semiconductor technology advancing, the size of transistors and their operating voltage keep decreasing. One of the major problems with advanced semiconductor technology is timing errors caused by process variation and device aging. With such problems, conventional worst-case designs suffer poor system performance.
This thesis proposes an aggressive design technique for VLSI digital filters for tolerating multiple timing errors. We have developed a methodology of designing reconfigurable VLSI digital filters that can tolerate multiple timing errors. The reconfigurable digital filters are resilient to any timing errors occurring at any stage and any time. When the timing error occurs, the system reconfigures the buffer cells of digital filters with little performance degradation.
We have applied the technique to two example digital filter designs, including an FIR filter and an IIR filter. The implementation results show that our proposed designs achieve tolerance of multiple timing errors with reasonable cost.

目錄
第一章 導論
1.1研究動機與目的 1
1.2時序錯誤與容錯電路 1
1.3論文架構 2
第二章 相關研究
2.1 Razor架構 5
2.2 RazorII架構 6
2.3 T-error架構 7
第三章 容忍多重時序錯誤電路設計
3.1設計目標 9
3.2電路架構 9
3.2.1 三個正反器組織的管線緩衝區 10
3.2.2兩個正反器組織的管線緩衝區 14
3.2.3 控制電路 17
3.3各種路徑電路 18
3.3.1 Linear路徑電路 18
3.3.2 Forward路徑電路 20
3.3.3 Feedback路徑電路 26
3.4應用於DSP電路 28
3.4.1綜合電路應用 28
3.4.2實際電路範例 30
第四章 實作測試與數據
4.1 Verilog模擬 35
4.1.1 Linear電路模擬 35
4.1.2 Forward電路模擬 37
4.1.3 Feedback 電路模擬 39
4.1.4綜合電路模擬 40
4.1.5實際電路模擬 41
4.2合成與佈局結果 42
4.2.1 Control電路數據 43
4.2.2 Stall電路數據 43
4.2.3 範例FIR電路數據 44
4.2.4 範例IIR電路數據 47
4.3 合成後之電路數據比較 50
第五章 結論
參考文獻 55

[1] H. Asadi and M.B. Tahoori, “Soft Error Hardening for Logic-Level Designs,” Proceedings of IEEE International Symposium on Circuits and Systems, pp. 4139-4142, May 2006.
[2] S.W. Chan and C.L. Wey, “The Design of Concurrent Error Diagnosable Systolic Arrays for Band Matrix Multiplications,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 21-37, 1988.
[3] M. Fazeli, A. Patooghy, S.G. Miremadi, and A. Ejlali, “Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies,” Proceedings of IEEE/IFIP International Conference on Dependable Systems and Networks, June 2007, pp. 276-285.
[4] A. Floros, Y. Tsiatouhas, A. Arapoyanni and Th. Haniotakis, “A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism,” Proceedings of 13th IEEE International Conference on Electronics Circuits and Systems, December, 2006, pp.692-695.
[5] S. Ghosh and K. Roy, “Parameter Variation Tolerance and Error Resiliency:
New Design Paradigm for the Nanoscale Era,” Proceedings of the IEEE, Oct. 2010, pp.1718-1751.
[6] A. Goel, S. Bhunia, H. Mahmoodi, and K. Roy, “Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flops with Enhanced-Scan Capability,” Proceedings of Asia and South Pacific Conference on Design Automation, Jan. 2006, pp. 24-27.
[7] R. Guo and S. Venkataraman, “A Technique for Fault Diagnosis of Defects in Scan Chains,” Proceedings of IEEE International Test Conference, Nov. 2001, pp. 268-277.
[8] Y. Huang, W.T. Cheng, S.M. Reddy, C.J. Hsieh, and Y.T. Hung, “Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault,” Proceedings of IEEE International Test Conference, Sept. 2003, pp. 319-328.
[9] R.K. Iyer, N.M Nakka, Z.T. Kalbarczyk and S. Mitra, “Recent Advances and New Avenues in Hardware-Level Reliability Support,” IEEE Micro, Vol. 25, No. 6, 2005, pp. 18-29.
[10] H.T. Kung and C.E. Leiserson, “Algorithms for VLSI Processor Arrays,” Ch8: Systems VLSI, July 1978.
[11] R. Tamhankar, S. Murali, S. Stergiou, A. Pullini, F. Angiolini, L. Benini, and G.D. Micheli, “Timing-Error-Tolerant Network-on-Chip Design Methodology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July 2007, pp. 1297-1310.
[12] Y. Wu, “Diagnosis of Scan Chain Failures,” Proceedings of IEEE International Symposium on Defect and Fault Tolerance VLSI Systems, Nov. 1998 pp. 217-220,.
[13] J.C.M. Li, “Diagnosis of Single Stuck-at Faults and Multiple Timing Faults in Scan Chains,” IEEE Transactions on VLSI, June 2005, pp. 708-718.
[14] M. Zhang, S. Mitra, T.M. Mask, N. Seifert, N.J. Wang, Q. Shi, and K.S. Kim, “Sequential Element Design with Built-In Soft Error Resilience,” IEEE Transactions on VLSI, Dec. 2006, pp.1368-1378.
[15] D. Ernst, S. Pant, R. Rao, C. Ziesler, D. Blaauw, T. Austin, K. Floutner, and T. Mudge, “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation,” Proceedings of Annual IEEE/ACM International Symposium on Microarchitecture, 2003, pp. 7-18.
[16] S. Valadimas, Y. Tsiatouhas, and A. Arapoyanni, “Timing error tolerance in nanometer ICs,” IEEE 16th International on-Line Testing Symposium, July 2010, pp. 283-288.
[17] S. Das, C. Tokunaga, S. Pant, W.-H. Ma, S. Kalaiselvan, K. Lai, D. Bull,
and D. Blaauw, “RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance,” IEEE Journal Solid-State Circuit, vol. 44, no. 1,Jan. 2009, pp. 32–48.
[18] Y. Lin and M. Zwolinski, “SETTOFF: A Fault Tolerant Flip-Flop for Building Cost-efficient Reliable Systems,” IEEE 18th International On-Line Testing Symposium, pp. 7–12,2012.