臺灣博碩士論文加值系統

目前非揮發性記憶體在元件尺寸持續的微縮下，其需求為高密度記憶單元、低功率損耗、快速讀寫操作以及良好的可靠度(Reliability)。然而傳統浮動閘極(Floating gate)記憶體在操作過程中，穿遂氧化層產生漏電路徑會造成所有儲存電荷流失回到矽基板，隨著尺寸微縮這種情況會更趨嚴重，所以在資料保存時間(Retention)和抗劣化程度(Endurance)的考量下，微縮穿遂氧化層的厚度是非常困難的。在眾多新興的記憶體結構中，由於其簡單的原件結構及優越的操作性能及可微縮性，具非揮發性電阻式記憶體被提出並希望可取代傳統浮動閘極記憶體。
在本論文中，藉由發現與探討以二氧化矽為基底的電阻式記憶體元件結構特性與操作機制，並藉由電性操作及結構改變的方式更進一步地改善其電阻切換特性。我們首先藉由製作厚度為20 nm之鉬摻雜二氧化矽薄膜結構之電阻式記憶體元件，並發現其切換特性主要為二氧化矽薄膜所主導。接著我們試著探討導致二氧化矽薄膜不易發現電阻切換特性的原因。我們發現，當二氧化矽薄膜厚度高於20 nm 後，其於活化過程(Forming process)所產生的氧離子於驅趕至氮化鈦電極的過程會受到限致，導致部分的氧離子由於無法順利排出薄膜外而與通道上的氧空缺進行再次結合(Recombination)，因而形成了一層非預期的「再形成二氧化矽層」(Reformed SiO2 layer)，使的薄膜的活化失敗，故無法觀察到電阻切換行為。而我們也成功地利用於薄膜活化時升高環境溫度的方式，增加氧離子的移動速率，進而改善活化失敗的問題。
此外，為了達到低功耗的目的，元件的操作電流一直是電阻式記憶體所努力研究改善的課題之一。而我們發現電阻式記憶體的切換特性會受到活化過程時的環境溫度所影響。當活化過程執行時的環境溫度越高，會使元件於切換時能夠有較低的高阻態電流 (HRS current)。探究其原因是由於，高溫的環境會使的元件於崩潰活化的過程中造成較嚴重的破壞，因而相對地產生較多的自由氧離子可於回抹(Reset)過程時，對通道產生較好的修復特性，因而抑制其漏電行為。而我們也同樣地利用在釩摻雜二氧化矽薄膜及氮化鈦電極間額外再加入一層3 nm 厚的非晶矽層的結構成功地抑制了低電阻態的電流(LRS current)。主要原因是由於在設置(Set)過程中，釩摻雜二氧化矽薄膜內的氧離子會受電場驅動而往氮化鈦電極方向移動，而此矽崁入層會補獲這些氧離子而氧化成二氧化矽薄膜，導致能障增加，不利其電子傳導，故能達到電流抑制的效果。
最後，我們藉由Agilent B1500 搭配 B1530的快速量測系統 (Fast I-V) 對純二氧化矽薄膜施加一-2 V的脈衝訊號去模擬直流(DC)操作時的回抹過程，並同時觀察脈衝電壓訊號期間所產生的對應電流訊號來對整個元件回抹過程的行為做分析。我們發現，回抹過程可簡單的分成三個行為區域，分別是「歐姆區(Ohmic Region)」、「回抹區(Reset Region)」和「穩定區(Stable Region)」。由於薄膜(通道)修復行為主要發生在「回抹區」，因此此區為主要的分析重點。當偏壓超過回抹電壓(Reset voltage)後，元件行為即進入「回抹區」。此時，大量的氧離子被驅趕進薄膜內進行通道修補，因此會產生較劇烈的修復現象，使得電阻隨電壓線性增加而呈指數增加。之後，由於切換層(Switching layer)已形成使的氧離子被驅趕進薄膜內的效果降低，導致修復現象逐漸趨緩，故電阻改呈線性增加。且藉由分析此線性關係，我們可獲得一個元件的最小回抹位能(Potential energy of reset)為0.26 V，我們利用此分析結果成功地回推出回抹電壓，因而可驗證此數值的合理性與正確性。另外，在回抹過程中，切換層除了會因氧離子的回填而形成外，也會由於偏壓的增加而發生崩潰破壞的現象。當崩潰行為發生後，氧離子便能夠被驅趕進薄膜內更深的區域來對通道做修補，因而使切換層的形成區域(薄膜的修復區域)更大，進而造成薄膜漏電流能夠繼續降低，並達到更高的阻態。
目前在很多材料中，均有發現電阻切換特性的存在。而為了提高商業化應用的可能性，找到便宜、豐富且熟悉的物質做為電阻式記憶體的材料是目前的當務之急，而二氧化矽電阻切換行為特性的發現想必對電阻式記憶體的發展是一大福音。另外，本論文中對電阻式記憶體切換機制的研究以其操作特性的改善皆為促使電阻式記憶體商品化所不可忽視的課題。

Current requirements of nonvolatile memory (NVM) are the high density cells, low-power consumption, high-speed operation and good reliability for next-generation NVM application. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVM during endurance test. Therefore, the tunnel oxide thickness is difficult to scale down in terms of charge retention and endurance characteristics. Among the emerging memory structure, resistive random access memory (ReRAM) has attract extensive attention as the promising candidates to substitute for conventional floating gate memory due to its sample structure, superior and scalable properties.
In this thesis, the memory phenomenon and mechanisms for the SiO2 based ReRAM are obtained and investigated. The switching characteristics are improved through the electric post-treatment and structure modulation methods. The ReRAM device was fabricated by depositing a 20 nm-thick Mo:SiO2 film as the active layer. It is discovered that the switching characteristics for the Mo:SiO2 device are dominated by the SiO2. Subsequently, the reasons which cause the switching characteristics for SiO2 are reported rarely are investigated. We find that the oxygen ions generated during the forming process would be limited by the driven ability while the thickness of the SiO2 film gets larger than 20 nm. The extra oxygen ions accumulate at the interface of SiO2/TiN. Afterward, the unexpected reformed SiO2 layer (RFL) is formed to blockade the conductive filament (CF) due to the recombination of the extra oxygen ions and the oxygen vacancies. As a result, the failure in the film activation by the forming process leads to the visible of the switching phenomenon in the SiO2 film. The problem is solved successfully by rising the temperature ambient during the forming process.
In order to achieve the target of low power consumption, reducing the operation current is one of the concerned topics for the research in ReRAM. We discover that the switching characteristics can be affected by the temperature ambient during the forming process. The high resistance state (HRS) current decreases when the temperature ambient increases during the forming process. The phenomenon can be attributed to that more oxygen ions are generated due to the high temperature ambient induced serious damage during the forming process. As a result, the CF can be well repaired by the assistance of the more oxygen ions. The formation of the well-repaired CF leads to the reduction of the HRS current. The low resistance state (LRS) current is also suppression successfully by inserting a 3 nm-thick Si layer between the V:SiO2 active layer and the TiN electrode. Since the Si inserted layer can gather the oxygen ions driven form the V:SiO2 film during the set process, the Si inserted layer transform to the SiO2 layer in LRS. The formation of the SiO2 layer increases the barrier for the carrier transport. Hence, the LRS current is suppressed.
Finally, a -2 V pulse voltage signal is applied to the SiO2 film to simulate the DC condition operated during the reset process. According to utilize B1500 and B1530 semiconductor characterization analyzer, the responding current among the whole voltage pulse period can be obtained and analyzed. The analyzed results present that the reset process can be divided into three parts, i.e. “Ohmic Region”, “Reset Region”, and “Stable Region”. Since the repair behavior of the film (CF) mainly occurs in Reset Region, the analyses of the reset process are focused on this region. When the bias is applied large above the reset voltage (Vreset), the reset process enters the Reset Region. Numerous oxygen ions are suddenly released and driven into the film at the moment of achieving the Vreset. An exponential increase in the resistance is exhibited in the initial of the Reset Region due to the extensive repair caused by these numerous oxygen ions. Afterward, the repair behavior is suppressed by the formation of the SL. The resistance increases linearly instead. Through analyzing the linear relation characteristic, the potential energy of reset is obtained as 0.26 V. By utilizing the parameters to estimate the Vreset value, the validity of these parameters can be confirmed. In addition, breakdown behavior also occurs besides repair behavior for the dielectric film and the SL during the reset process. Oxygen ions can be driven farther and further repairs the film and the CF while the breakdown behavior is induced. Subsequently, the thickness or area of the SL gets larger which leads to the suppression of leakage current and the increase in the resistant state.
The resistive switching phenomenon has been discovered in a number of materials. In order to promote the commercial application of ReRAM, it is important to find the cheap, abound and familiar material as the active layer. The discovery of resistive switching phenomenon in the SiO2 is helpful for the development of the ReRAM device. In addition, the investigation of the switching mechanisms and the improvement of the switching characteristics studied in this thesis are also significant for the promotion of the commercial application of ReRAM.

Contents
Acknowledgement----------------------------------------------------------------i
Chinese Abstract-----------------------------------------------------------------iv
English Abstract----------------------------------------------------------------vii
Contents---------------------------------------------------------------------------xi
Figure Captions-----------------------------------------------------------------xv
Table Captions-----------------------------------------------------------------xxv

Chapter 1 Introduction
1.1 Overview of Nonvolatile Memory --------------------------------------1
1.1.1 FeRAM (Ferroelectric Random Access Memory--------------------------3
1.1.2 PCRAM (Phase Change Random Access Memory)-----------------------4
1.1.3 MRAM (Magnetic Random Access Memory)-----------------------------5
1.1.4 ReRAM (Resistive Random Access Memory)---------------------------6
1.2 Motivation------------------------------------------------------------------------7
1.3 Organization of This Thesis-----------------------------------------------8

Chapter 2 Basic Principle of ReRAM Nonvolatile Memory
2.1 Introduction---------------------------------------------------------------------14
2.2 The Switching Mechanism of ReRAM ------------------------------15
2.2.1 Schottky barrier model (Interfacial-type model-------------------------16
2.2.2 Charge-trap model-----------------------------------------------------------16
2.2.3 Filamentary model (bulk-type model)------------------------------------17
2.3 The transport mechanism of carriers--------------------------------20
2.3.1 Ohmic conduction mechanism---------------------------------------------20
2.3.2 Schottky emission (Thermal emission) mechanism--------------------21
2.3.2 Poole-Frenkel emission mechanism---------------------------------------21
2.3.2 Tunneling conduction mechanism-----------------------------------------22
2.3.2 Space charge limited current mechanism---------------------------------23
2.4 Basic Reliability of Nonvolatile Memory----------------------------23
2.4.1 Retention--------------------------------------------------------------------24
2.4.2 Endurance--------------------------------------------------------------------24
2.4.2 Reading disturbance---------------------------------------------------25

Chapter 3 Resistive Switching Behavior on SiO2 film for Nonvolatile Memory Application
3.1 Influence of molybdenum doping on the switching characteristic in silicon oxide-based resistive switching memory
3.1.1 Introduction------------------------------------------------------------------34
3.1.2 Experiment-------------------------------------------------------------------35
3.1.3 Results and discussion------------------------------------------------------35
3.1.4 Conclusion-------------------------------------------------------------------38
3.2 Thermal impact on the activation of resistive switch in silicon oxide based ReRAM
3.2.1 Introduction------------------------------------------------------------------39
3.2.2 Experiment-------------------------------------------------------------------40
3.2.3 Results and discussion------------------------------------------------------40
3.2.4 Conclusion-------------------------------------------------------------------42

Chapter 4 Improvement on the Resistive Switching Characteristics of SiO2 film
4.1 Improvement of resistive switching characteristics by thermally assisted forming process for SiO2-based structure
4.1.1 Introduction------------------------------------------------------------------56
4.1.2 Experiment-------------------------------------------------------------------57
4.1.3 Results and discussion------------------------------------------------------57
4.1.4 Conclusion-------------------------------------------------------------------60
4.2 Operation Current Reduction in Vanadium doped SiO2-based ReRAM
4.2.1 Introduction------------------------------------------------------------------62
4.2.2 Experiment-------------------------------------------------------------------62
4.2.3 Results and discussion------------------------------------------------------63
4.2.4 Conclusion-------------------------------------------------------------------65
4.3 Insertion of a Si layer to reduce operation current for resistive random access memory (ReRAM) applications
4.2.5 Introduction------------------------------------------------------------------66
4.2.6 Experiment-------------------------------------------------------------------66
4.2.7 Results and discussion------------------------------------------------------67
4.2.8 Conclusion-------------------------------------------------------------------69

Chapter 5 Investigation on the switching mechanisms for SiO2 ReRAM
5.1 Analyses of the Reset behavior by Fast I-V Measurement for SiO2 ReRAM
5.1.1 Introduction------------------------------------------------------------------93
5.1.2 Experiment-------------------------------------------------------------------94
5.1.3 Results and discussion------------------------------------------------------94
5.1.4 Conclusion-------------------------------------------------------------------97

Chapter 6 Conclusion-------------------------------------------------------106
References-----------------------------------------------------------------------108
Paper list-------------------------------------------------------------------------125

Reference
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[3.25]F. M. Yang, T. C. Chang, P. T. Liu, P. H. Yeh, Y. C. Yu, J. Y. Lin, S. M. Sze, and J. C. Lou, “Memory characteristics of Co nanocrystal memory device with HfO2 as blocking oxide,” Appl. Phys. Lett., 90, 132102 (2007).
[3.26]T. C. Chen, T. C. Chang, F. Y. Jian, S. C. Chen, C. S. Lin, M. H. Lee, J. S. Chen, and C. C. Shih, “Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in aSONOS-TFT Memory Device,” IEEE Trans. Electron Device Lett., 30 (8), 834 (2009).
[3.27]X. Liu, K. P. Biju, E. M. Bourim, S. Park, W. Lee, D. Lee, K. Seo, and H. Hwang, “Filament-Type Resistive Switching in Homogeneous Bi-Layer Pr0.7Ca0.3MnO3 Thin Film Memory Devices,” Electrochem. Solid-State Lett., 14 (1), H9 (2011).
[3.28]D. Choi, D. Lee, H. Sim, M. Chang, and H. Hwang, “Reversible resistive switching of SrTiOx thin films for nonvolatile memory applications,” Appl. Phys. Lett., 88, 082904 (2006).
[3.29]S. C. Chen, T. C. Chang, S. Y. Chen, H. W. Li, Y. T. Tsai, C. W. Chen, S. M. Sze, F. S. Yeh(Huang), and Y. H. Tai, “Carrier Transport and Multilevel Switching Mechanism for Chromium Oxide Resistive Random-Access Memory,” Electrochem. Solid-State Lett., 14 (2), H103 (2011).
[3.30]Y. T. Tsai, T. C. Chang, W. L. Huang, C. W. Huang, Y. E. Syu, S. C. Chen, S. M. Sze, M. J. Tsai, and T. Y. Tseng, “Investigation for coexistence of dual resistive switching characteristics in DyMn2O5 memory devices,” Appl. Phys. Lett., 99, 132104 (2011).
[3.31]T. Y. Lin, L. M. Chen, S. C. Chang, and T. S. Chin, “Electrical resistance switching in Ti added amorphous SiOx, Appl. Phys. Lett., 95, 162105 (2009).
[3.32]Y. E. Syu, T. C. Chang, C. T. Tsai, G. W. Chang, T. M. Tsai, K. C. Chang, Y. H. Tai, M. J. Tsai, and S. M. Sze, “Improving Resistance Switching Characteristics with SiGeOx/SiGeON Double Layer for Nonvolatile Memory Applications,” Electrochem. Solid-State Lett., 14 (10), H419 (2011).
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Chapter 4
[4.1]F. M. Yang, T. C. Chang, P. T. Liu, P. H. Yeh, Y. C. Yu, J. Y. Lin, S. M. Sze, and J. C. Lou, “Memory characteristics of Co nanocrystal memory device with HfO2 as blocking oxide,” Appl. Phys. Lett., 90, 132102 (2007).
[4.2]J. Lu, T. C. Chang, Y. T. Chen, J. J. Huang, P. C. Yang, S. C. Chen, H. C. Huang, D. S. Gan, N. J. Ho, Y. Shi, and A. K. Chu, “Enhanced retention characteristic of NiSi2/SiNx compound nanocrystal memory,” Appl. Phys. Lett., 96, 262107 (2010).
[4.3]T. C. Chang, F. Y. Jian, S. C. Chen, Y. T. Tsai, “Developments in nanocrystal memory,” Mater. Today, 14 (12), 526 (2011).
[4.4]S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, P. S. Lin, B. H. Tseng, J. H. Shy, S. M. Sze, C. Y. Chang, and C. H. Lien, “A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory,” IEEE Electron Device Lett., 28 (9), 809 (2002).
[4.5]T. C. Chen, T. C. Chang, F. Y. Jian, S. C. Chen, C. S. Lin, M. H. Lee, J. S. Chen, and C. C. Shih, “Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in a SONOS-TFT Memory Device,” IEEE Electron Device Lett., 30 (8), 834 (2009).
[4.6]H. Y. Lee, P. S. Chen, T. Y. Wu, C. C. Wang, P. J. Tzeng, C. H. Lin, F. Chen, M. J. Tsai, and C. H. Lien, “Electrical evidence of unstable anodic interface in Ru/HfOx/TiN unipolar resistive memory,” Appl. Phys. Lett., 92, 142911 (2008).
[4.7]M. C. Chen, T. C. Chang, S. Y. Huang, S. C. Chen, C. W. Hu, C. T. Tsai, and S. M. Sze, “Bipolar Resistive Switching Characteristics of Transparent Indium Gallium Zinc Oxide Resistive Random Access Memory,” Electrochem. Solid-State Lett., 13 (6), H191 (2010).
[4.8]J. J. Huang, C. W. Kuo, W. C. Chang, and T. H. Hou, “Transition of stable rectification to resistive-switching in Ti/TiO2/Pt oxide diode,” Appl. Phys. Lett., 96, 262901 (2010).
[4.9]C. T. Tsai, T. C. Chang, P. T. Liu, Y. L. Cheng, and F. S. Huang, “Low temperature improvement on silicon oxide grown by electron-gun evaporation for resistance memory,” Appl. Phys. Lett., 93, 052903 (2008).
[4.10]T. Y. Lin, L. M. Chen, S. C. Chang, and T. S. Chin, “Electrical resistance switching in Ti added amorphous SiOx,” Appl. Phys. Lett., 95, 162105 (2009).
[4.11]H. C. Tseng, T. C. Chang, J. J. Huang, P. C. Yang, Y. T. Chen, F. Y. Jian, S. M. Sze, and M. J. Tsai, “Investigating the improvement of resistive switching trends after post-forming negative bias stress,” Appl. Phys. Lett., 99, 132104 (2011).
[4.12]Y. E. Syu, T. C. Chang, T. M. Tsai, G. W. Chang, K. C. Chang, Y. H. Tai, M. J. Tsai, Y. L. Wang, and S. M. Sze, “Silicon introduced effect on resistive switching characteristics of WOX thin films,” Appl. Phys. Lett., 95, 022904 (2012).
[4.13]S. M. Sze, Physics of Semiconductor Devices, 2nd ed., Wiley, New York 1981, pp. 154-236.
[4.14]Y. T. Chen, T. C. Chang, J. J. Huang, H. C. Tseng, P. C. Yang, A. K. Chu, J. B. Yang, M. J. Tsai, Y. L. Wang, and S. M. Sze, “Thermal impact on the activation of resistive switch in silicon oxide based RRAM,” ECS Solid State Letters, 1 (4), 57 (2012).
[4.15]X. Guan, S. Yu, and H.-S. P. Wong, “On the Switching Parameter Variation of Metal-Oxide RRAM—Part I: Physical Modeling and Simulation Methodology,” IEEE Trans. Elecrron Devices, 59 (4), 1172 (2012).
[4.16]Z. Fang, H. Y. Yu, W. J. Liu, Z. R. Wang, X. A. Tran, B. Gao, and J. F. Kang, “Temperature Instability of Resistive Switching on HfOx-Based RRAM Devices,” IEEE Electron Device Lett., 31 (5), 476 (2010).
[4.17]T. C. Chen, T. C. Chang, C. T. Tsai, T. Y. Hsieh, S. C. Chen, C. S. Lin, M. C. Hung, C. H. Tu, J. J. Chang, and P. L. Chen, “Behaviors of InGaZnO thin film transistor under illuminated positive gate-bias stress,” Appl. Phys. Lett., 97, 112104 (2010).
[4.18]C. T. Tsai, T. C. Chang, S. C. Chen, I. Lo, S. W. Tsao, M. C. Hung, J. J. Chang, C.Y. Wu, and C. Y. Huang, “Influence of positive bias stress on N2O plasma improved InGaZnO thin film transistor,” Appl. Phys. Lett., 96, 242105 (2010).
[4.19]H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, F. Chen, C. C. Wang, P. J. Tzeng, C. H. Lin, M. J. Tsai, and C. Lien, “HfOx Bipolar Resistive Memory With Robust Endurance Using AlCu as Buffer Electrode,” IEEE Electron Device Lett., 30 (7), 703 (2009).
[4.20]Q. Liu, W. Guan, S. Long, M. Liu, S. Zhang, Q. Wang, and J. Chen, “Resistance switching of Au-implanted-ZrO2 film for nonvolatile memory application,” J. Appl. Phys., 104, 114514 (2008).
[4.21]M. C. Chen, T. C. Chang, C. T. Tsai, S. Y. Huang, S. C. Chen, C. W. Hu, S. M. Sze, and M. J. Tsai, “Influence of electrode material on the resistive memory switching property of indium gallium zinc oxide thin films,” Appl. Phys. Lett., 96, 262110 (2010).
[4.22]S. H. Jo, K. H0 Kim, and W. Lu, “Programmable Resistance Switching in Nanoscale Two-Terminal Devices,” Nano Lett., 9 (1), 496 (2009).
[4.23]J. J. Huang, T. C. Chang, J. B. Yang, S. C. Chen, P. C. Yang, Y. T. Chen, H. C. Tseng, S. M. Sze, A. K. Chu, and M. J. Tsai, “Influence of Oxygen Concentration on Resistance Switching Characteristics of Gallium Oxide,” IEEE Electron Device Lett., 33 (10), 1387 (2012).
[4.24]S. B. Lee, A. Kim, J. S. Lee, S. H. Chang, H. K. Yoo, T. W. Noh, B. Kahng, M. J. Lee, C. J. Kim, and B. S. Kang, “Reduction in high reset currents in unipolar resistance switching Pt/SrTiOx /Pt capacitors using acceptor doping,” Appl. Phys. Lett., 97, 093505 (2010).
[4.25]S. Y. Wang, D. Y. Lee, T. Y. Huang, J. W. Wu and T. Y. Tseng, “Controllable oxygen vacancies to enhance resistive switching performance in a ZrO2-based RRAM with embedded Mo layer,” Nanotechnology, 21, 495201 (2010).
[4.26]H. Zhang, L. Liu, B. Gao, Y. Qiu, X. Liu, J. Lu, R. Han, J. Kang, and B. Yu, “Gd-doping effect on performance of HfO2 based resistive switching memory devices using implantation approach,” Appl. Phys. Lett., 98, 042105 (2011).
[4.27]S. Cheylan, R. G. Elliman, K. Gaff, A. Durandet, “Luminescence from Si nanocrystals in silica deposited by helicon activated reactive evaporation,” Appl. Phys. Lett., 78 (12), 1670 (2001).
[4.28]D. Choi, G. E. Blomgren, and P. N. Kumta, “Fast and reversible surface redox reaction in nanocrystalline vanadium nitride supercapacitors,” Adv. Mater., 18, 1178 (2006).
[4.29]X. Qi, J. Dho, R. Tomov, M. G. Blamire, and J. L. MacManus-Driscoll, “Greatly reduced leakage current and conduction mechanism in aliovalent-ion-doped BiFeO3,” Appl. Phys. Lett., 86, 062903 (2005).
[4.30]H. Sun, J. Zhu, and H. Fang, “Large remnant polarization and excellent fatigue property of vanadium-doped SrBi4Ti4O15 thin films,” J. Appl. Phys., 100, 074102 (2006).
[4.31]L. Zhao, J. Zhang, Y. He, X. Guan, H. Qian, and Z. Yu, “Dynamic modeling and atomistic simulations of SET and RESET operations in TiO2-Based unipolar resistive memory,” IEEE Electron Device Lett., 32, 677 (2011).
[4.32]L. Zhang, R. Huang, D. Gao, D. Wu, Y. Kuang, P. Tang, W. Ding, A. Z. H. Wang, Y. Wang, “Unipolar resistive switch based on silicon monoxide realized by CMOS technology,” IEEE Electron Device Lett., 30, 870 (2009).
[4.33]K. C. Chang, T. M. Tsai, T. C. Chang, Y. E. Syu, C. C. Wang, S. L. Chuang, C. H. Li, D. S. Gan, and S. M. Sze, “Reducing operation current of Ni-doped silicon oxide resistance random access memory by supercritical CO2 fluid treatment,” Appl. Phys. Lett., 99, 263501 (2011).
[4.34]Z. J. Liu, J. Y. Gan, and T. R. Yew, “ZnO-based one diode-one resistor device structure for crossbar memory applications,” Appl. Phys. Lett., 100, 153503 (2012).
[4.35]Y. S. Chen, H. Y. Lee, P. S. Chen, W. H. Liu, S. M. Wang, P. Y. Gu, Y. Y. Hsu, C. H. Tsai, W. S. Chen, F. Chen, M. J. Tsai, and C. Lien, “Robust high-resistance state and improved endurance of HfOX resistive memory by suppression of current overshoot,” IEEE Electron Device Lett., 32, 1585 (2011).
[4.36]C. Y. Lin, C. Y. Wu, C. Y. Wu, T. Y. Tseng, C. Hu, “Modified resistive switching behavior of ZrO2 memory films based on the interface layer formed by using Ti top electrode,” J. Appl. Phys., 102, 094101 (2007).
[4.37]Y. Sato, K. Tsunoda, K. Kinoshita, H. Noshiro, M. Aoki, and Y. Sugiyama, “Sub-100-μA reset current of nickel oxide resistive memory through control of filamentary conductance by current limit of MOSFET,” IEEE Trans. Elecrron Devices, 55, 1185 (2008).
[4.38]J. J. Huang, Y. M. Tseng, W. C. Luo, C. W. Hsu, and T. H. Hou, “One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications,” IEDM Tech. Dig., 733 (2011).

[4.39]J. Shin, I. Kim, K. P. Biju, M. Jo, J. Park, J. Lee, S. Jung, W. Lee, S. Kim, S. Park, and H. Hwang, “TiO2-based metal-insulator-metal selection device for bipolar resistive random access memory cross-point application,” J. Appl. Phys., 109, 033712 (2011).
[4.40]D. Lee, J. Park, S. Jung, G. Choi, J. Lee, S. Kim, J. Woo, M. Siddik, E. Cha, and H. Hwang, “Operation voltage control in complementary resistive switches using heterodevice,” IEEE Electron Device Lett., 33, 600 (2012).



Chapter 5
[5.1]F. M. Yang, T. C. Chang, P. T. Liu, P. H. Yeh, Y. C. Yu, J. Y. Lin, S. M. Sze, and J. C. Lou, “Memory characteristics of Co nanocrystal memory device with HfO2 as blocking oxide,” Appl. Phys. Lett., 90, 132102 (2007).
[5.2]S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, P. H. Yeh, C. F. Weng, S. M. Sze, C. Y. Chang, and C. H. Lien, “Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels,” Appl. Phys. Lett., 90, 122111 (2007).
[5.3]J. Lu, T. C. Chang, Y. T. Chen, J. J. Huang, P. C. Yang, S. C. Chen, H. C. Huang, D. S. Gan, N. J. Ho, Y. Shi, and A. K. Chu, “Enhanced retention characteristic of NiSi2/SiNx compound nanocrystal memory,” Appl. Phys. Lett., 96, 262107 (2010).
[5.4]L. Goux, P. Czarnecki, Y. Y. Chen, L. Pantisano, X. P. Wang, R. Degraeve, B. Govoreanu, M. Jurczak, D. J. Wouters, and L. Altimime, “Evidences of oxygen-mediated resistive-switching mechanism in TiNHfO2Pt cells,” Appl. Phys. Lett., 97, 243509 (2010).
[5.5]C. Y. Lin, C. Y. Wu, C. Y. Wu, C. Hu, and T. Y. Tseng, “Bistable Resistive Switching in Al2O3 Memory Thin Films,” J. Electrochem Soc.,154, G189 (2007).
[5.6]H. C. Tseng, T. C. Chang, K. H. Cheng, J. J. Huang, Y. T. Chen, F. Y. Jian, S. M. Sze, M. J. Tsai, A. K. Chu, Y. L. Wang, “Investigating bipolar resistive switching characteristics in filament type and interface type BON-based resistive switching memory,” Thin Solid Films, 529, 389 (2013).
[5.7]C. T. Tsai, T. C. Chang, P. T. Liu, Y. L. Cheng, and F. S. Huang, “Low temperature improvement on silicon oxide grown by electron-gun evaporation for resistance memory,” Appl. Phys. Lett., 93, 052903 (2008).
[5.8]T. Y. Lin, L. M. Chen, S. C. Chang, and T. S. Chin, “Electrical resistance switching in Ti added amorphous SiOx,” Appl. Phys. Lett., 95, 162105 (2009).
[5.9]Y. S. Chen, H. Y. Lee, P. S. Chen, W. H. Liu, S. M. Wang, P. Y. Gu, Y. Y. Hsu, C. H. Tsai, W. S. Chen, F. Chen, M. J. Tsai, and C. Lien, “Robust high-resistance state and improved endurance of HfOX resistive memory by suppression of current overshoot,” IEEE Electron Device Lett., 32, 1585 (2011).