臺灣博碩士論文加值系統

為了提升微處理器的效能及其應用，將管線運算核心、例外控制單元、快取記憶體單元及記憶體管理單元整合到微處理器是必須的，針對微處理器整合驗證，作業系統是一套有效的方法，然而直接以移植作業系統的方式進行驗證會造成除錯上的困難，因為當作業系統執行崩潰時，我們沒辦法以目前執行崩潰的資訊推測其正確的執行失敗點，進行有效的除錯。
經由分析作業系統，我們發現資料傳輸及例外處理是其主要的執行特性，基於這些執行特性，我們提出一套整合驗證方法，分別針對同步快取傳輸操作、連續快取傳輸操作、外部中斷例外處理、分頁錯誤例外處理及多種中斷例外處理進行驗證。我們於本實驗室發展之ARM7-Like微處理器進行實驗，經由提出之軟體驗證方法，可以有效的於RTL模擬期間檢測出微處理器整合錯誤點，進行有效的除錯。經過修正之ARM7-Like微處理器可以於FPGA驗證，可以成功地啟動Linux作業系統，並且執行使用者應用程式。

For improving the performance and application of microprocessor, it is necessary to integrate pipelined core, exception control unit, cache unit and memory management unit (MMU). The operating system is an effective way for microprocessor integration verification. However, it is not a feasible debugging methodology to detect the exact design bug while operating system booting crash. We found the main execution features of operating system are the data transfer and exception handling. We propose an integration verification methodology based on these execution features. The methodology is to verify concurrent cache transfer operation, consecutive cache transfer operation, external interrupt exception handling, page fault exception handling and multiple interrupt exception handling for microprocessor integration. We utilize ARM7-Like developed by our laboratory to do the experiment. It is effective to detect the design bugs in RTL simulation by the software-based verification methodology proposed by us. The modified ARM7-Like microprocessor is able to successfully boot Linux kernel and execute user applications in FPGA.

Chapter 1. Introduction 1
1.1. Background 1
1.2. Motivation 1
Chapter 2. Related work 2
2.1. Pipelined core verification 2
2.2. Exception/Interrupt verification 4
2.3. Cache verification 6
Chapter 3. Introduction of ARM7-Like microprocessor 8
3.1. Pipelined core 8
3.2. Cache unit 18
3.3. Memory management unit 20
Chapter 4. Integration verification for ARM7-Like microprocessor 30
4.1. Overview 30
4.2. Fault for cache transfer operation 32
4.2.1. Fault for concurrent cache transfer operation 32
4.2.2. Fault for consecutive cache transfer operation 34
4.3. Fault for pipelined core exception handling 36
4.3.1. Fault for external interrupt handling 36
4.3.2. Fault for data page fault handling 38
4.3.3. Fault for instruction page fault handling 41
4.3.4. Fault for multiple interrupt type 1 handling 43
4.3.5. Fault for multiple interrupt type 2 handling 46
Chapter 5. Linux porting for ARM7-Like microprocessor 50
5.1. U-Boot-1.1.4 50
5.2. Linux-2.6.29 kernel 51
5.3. Busybox-1.16.1 65
Chapter 6. Experimental results 67
6.1. RTL verification of ARM7-Like 67
6.2. Fault list and correction of ARM7-Like 73
6.3. FPGA verification of ARM7-Like 82
Chapter 7. Conclusion 86
Reference 87
Appendix A.U-boot patch list 89
Appendix B.Linux kernel patch list 93

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