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 近來，由於臨界邏輯電路在實作上的快速發展，一併帶動了許多臨界邏輯的相關研究，像是合成、驗證與測試等等。相較於以線性規劃為基底的合成演算法，我們提出了一個藉由重接線來減少臨界值邏輯電路實作成本的演算法。此外，我們也改善既有的臨界邏輯閘簡化演算法。臨界效應輸入向量是一個臨界邏輯閘輸入向量的子集，我們證明了臨界效應輸入向量足以驗證兩個臨界邏輯閘是否相等，不需要比較兩個臨界邏輯閘的真值表。而這也有效的加速了我們驗證臨界邏輯閘功能性所需的時間。
 Recently, there have been many works focusing on synthesis, verification, and testing of threshold circuits due to the rapid development in efficient implementation of threshold logic circuits. To minimize the hardware cost of threshold circuit implementation, this paper proposes a heuristic that consists of rewiring operations and a simplification procedure. Additionally, a subset of input vectors of a gate, called critical-effect vectors, are proved to be complete for formally verifying the equivalence of two threshold logic gates, instead of the whole truth table in this paper. This achievement can accelerate the equivalence checking of two threshold logic gates. The experimental results show that the proposed heuristic can efficiently reduce the implementation cost.
 1 Introduction2 Preliminaries 2.1 Threshold logic 2.2 Critical-effect vectors 2.3 Target wire removal and rectification network construction 2.4 Weight transformation3 Cost minimization algorithm 3.1 Overview 3.2 Target wire selection4 Simplification 4.1 Functional equivalence of two LTGs 4.2 Simplification overview 4.3 Simplification flow5 Experimental results6 Conclusion
 [1] M. J. Avedillo and J. M. Quintanaa, “A Threshold Logic Synthesis Tool for RTD Circuits," in Proc. European Symp. on Digital System Design, 2004, pp. 624-627.[2] M. J. Avedillo, J. M. Quintana, H. Pettenghi, P. M. Kelly, and C. J. Thompson, “Multi-Threshold Threshold Logic Circuit Design Using Resonant Tunnelling Devices," Electron. Lett., vol. 39, no. 21, Oct. 2003, pp. 1502-1504.[3] V. Beiu, J. M. Quintana, and M. J. Avedillo, “VLSI Implementations of Threshold Logic - a Comprehensive Survey," in Tutorial at Int. Joint Conf. Neural Networks, 2003.[4] S.-C. Chang, L.P.P.P. van Ginneken, and M. Marek-Sadowska, “Circuit Optimization by Rewiring," IEEE Trans. on Computers, 1999, pp. 962-970.[5] S.-C. Chang, L.P.P.P. van Ginneken, and M. Marek-Sadowska, “Fast Boolean Optimization by Rewiring," in Proc. Int. Conf. Computer-Aided Design, 1996, pp. 262-269.[6] Y.-C. Chen, Soumya Eachempati, C.-Y. Wang, Suman Datta, Yuan Xie, and Vijaykrishnan Narayanan, “A Synthesis Algorithm for Recongurable Single-Electron Transistor Arrays," ACM Journal on Emerging Technologies in Computing Systems, Vol. 9, No. 1, Article 5, Feb. 2013.[7] Y.-C. Chen and C.-Y. Wang, “Logic Restructuring Using Node Addition and Removal," IEEE Trans. on Computer-Aided Design, pp. 260-270, Feb. 2012.[8] Y.-C. Chen and C.-Y. Wang, “Fast Node Merging With Don't Cares Using Logic Implications," IEEE Trans. on Computer-Aided Design, pp. 1827-1832, Nov. 2010.[9] Y.-C. Chen and C.-Y. Wang, “Node Addition and Removal in the Presence of Don't Cares," in Proc. Design Automation Conf., 2010, pp. 505-510.[10] Y.-C. Chen and C.-Y. Wang, “Fast Detection of Node Mergers Using Logic Implications," in Proc. Int. Conf. on Computer-Aided Design, 2009, pp. 785- 788.[11] Y.-C. Chen and C.-Y. Wang, “An Improved Approach for Alternative Wire Identification," in Proc. Int. Conf. on Computer Design, 2005, pp. 711-716.[12] C.-E. Chiang, L.-F. Tang, C.-Y.Wang, C.-Y. Huang, Y.-C. Chen, Suman Datta and Vijaykrishnan Narayanan, “On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques," IEEE Design Automation and Test in Europe, pp. 1807-1812, Mar. 2013.[13] D. Goldharber-Gordon, M. S. Montemerlo, J. C. Love, G. J. Opiteck, and J. C. Ellenbogen. “Overview of Nanoelectronic Devices," in Proc. IEEE, pp. 521-540, Jan. 1997.[14] Goparaju, Manoj Kumar, “A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations," in Proc. Int. Symposium on Quality Electronic Design, 2007, pp. 420-425.[15] T. Gowda, S. Vrudhula, N. Kulkarni, and K. Berezowski, “Identification of Threshold Functions and Synthesis of Threshold Networks," IEEE Trans. On Computer-Aided Design, 2011, pp. 665-677.[16] T. Gowda, S. Vrudhula, and G. Konjevod, “Combinational Equivalence Checking for Threshold Logic Circuits," in Proc. Great Lake Symp. VLSI, 2007, pp. 102-107.[17] P. Gupta, R. Zhang, and N. K. Jha, “Automatic Test Generation for Combinational Threshold Logic Networks," IEEE Trans. Very Large Scale Integration Systems, pp.1035-1045, Aug. 2008.[18] P. Gupta, R. Zhang, and N. K. Jha, “An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks," in Proc. Int. Conf. on Computer-Aided Design, pp. 540-543, Oct. 2004.[19] C.-Y. Huang, D.-M. Lee, C.-C. Lin, and C.-Y. Wang, “Error Injection & Correction: An Efficient Formal Logic Restructuring Algorithm," in Proc. Int. SoC Design Conf., pp. 188-191, 2012.[20] P.-Y. Kuo, C.-Y. Wang, and C.-Y.Huang, “On Rewiring and Simplification for Canonicity in Threshold Logic Circuits," in Proc. Int. Conf. on Computer-Aided Design, pp. 396-403, Nov. 2011.[21] C. Lageweg, S. Cotofana, and S. Vassiliadis, “A Linear Threshold Gate Implementation in Single Electron Technology," in Proc. IEEE Computer Society Workshop on VLSI, 2001, pp. 93-98.[22] C.-C. Lin, and C.-Y. Wang, “Rewiring Using Irredundancy Removal and Addition," in Proc. Design Automation and Test in Europe, 2009, pp. 324-327.[23] K. Maezawa, H. Matsuzaki, M. Yamamoto, and T. Otsuji, “High-Speed and Low-Power Operation of A Resonant Tunneling Logic Gate MOBILE," IEEE Eletron Device Letters, vol. 19, pp.80-82, Mar. 1998.[24] S. Muroga, “Threshold Logic and its Applications". New York, NY: John Wiley,1971.[25] C. Pacha, P. Glosekotter, K. Goser, W. Prost, U. Auer, and F. Tegude, “Resonant Tunneling Device Logic Circuit," Dortmund/Gerhard-Mercator University of Duisburg, Germany, Tech. Rep., July 1999.[26] M. Perkowski and A. Mishchenko, “Logic Synthesis for Regular Fabric Realized in Quantum Dot Cellular Automata," in Proc. Int. J. Multiple-Valued Logic and Soft Comput., 2004, pp. 768-773.[27] V. Saripalli, L. Liu, S. Datta, and V. Narayanan, “Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits," J. Low Power Electron, 2010, pp. 415-428.[28] R. O. Winder, “Enumeration of Seven-Argument Threshold Functions," IEEE Trans. on Electronic Computers, 1965, pp. 315-325.[29] R. O. Winder, “Threshold Logic," Ph.D. dissertation, Princeton University, Princeton, NJ, 1962.[30] R. O. Winder, “Single Stage Threshold Logic," Switching Circuit Theory and Logical Design, pp. 321-332, Oct. 1961.[31] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, “Threshold Network Synthesis and Optimization and Its Application to Nanotechnologies," IEEE Trans. On Computer-Aided Design, pp. 107-118, Jan. 2005.[32] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, “Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies," in Proc. Design Automation and Test in Europe, 2004, pp. 904-909.[33] Y. Zheng, M. S. Hsiao, and C. Huang, “SAT-based Equivalence Checking of Threshold Logic Designs for Nanotechnologies," in Proc. Great Lake Symp. VLSI, 2008, pp. 225-230.[34] http://iwls.org/iwls2005/benchmarks.html
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 1 用於臨界值邏輯電路的重接線演算法及標準表示法的化簡方法

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