臺灣博碩士論文加值系統

雖然inductive peaking技術可以有效地提升頻寬，但是使用傳統被動式電感，需要大量的面積。為了減少晶片面積與成本，在論文中，主要探討兩項有線通訊微型化CMOS類比等化器之設計、模擬與量測。
首先， 本論文實現一個90奈米製程的20 Gb/s微型化類比等化器。為了補償3公尺長的同軸電纜線在10GHz的10dB損耗，此等化器混合使用摺疊式主動電感與電容/電阻源極退化的技術。比起傳統主動電感與被動式螺旋電感，摺疊式主動電感消耗比較少的壓降與面積。在提供1.2伏的電壓下，此等化器的功耗45 mW，面積僅佔0.14 × 0.28 mm2。在18、19和20 Gb/s量測到最大峰對峰抖動值，分別是14, 13, 15 ps。
接著，本論文設計另一個使用立體微型電感之20 Gb/s微型化類比等化器。立體微型電感的等效電容比立體堆疊式電感小很多。根據模擬顯示，在同樣電感值與面積之下，立體微型電感的自諧振頻率比立體堆疊式電感高過10GHz以上。此外，在相同電感值的情況，立體微型電感所佔的面積，比起被動式螺旋電感，小了至少1/36倍。因此，利用立體微型電感可以降低晶片的尺寸與成本。此電路使用90奈米製程與1.2伏電壓，功耗14 mW，面積僅佔0.21 × 0.26 mm2。

The inductive peaking technique is effective to broaden the bandwidth, but it requires a large chip area. In this thesis, two high speed miniaturized CMOS equalizers up to 20 Gb/s are proposed for wireline communications. The equalizers are discussed regarding the design, simulation, and measurement results.
Firstly, a 20 Gb/s miniaturized equalizer is realized in 90nm CMOS process. To compensate the coaxial cable loss of 10 dB (~ 3 meters) at 10 GHz, the equalizer incorporates folded active inductors with capacitive and resistive degeneration. Compared to the conventional active and spiral inductors, the folded active inductor consumes lower voltage and occupies less area. The circuit consumes 45mW from a 1.2 V supply, and only occupies 0.14 × 0.28 mm2. The measured maximum peak-to-peak jitter for 18, 19, and 20 Gb/s PRBSs are 14, 13, 15 ps, respectively.
Next, another 20 Gb/s miniaturized analog equalizer using 3D solenoid inductors is presented. The equivalent capacitance of the 3D solenoid inductor is much smaller than that of the typical stacked inductor. According to the measurement results, the self-resonance frequency of the 3D solenoid inductor exceeds that of the stacked inductor by 10 GHz with the same area and inductance. In addition, the area of the 3D solenoid inductor is 1/36 times smaller than that of the spiral inductor with the same inductance. Hence, utilizing the small area of 3D solenoid inductor can reduce the size of the chip and lower the cost. The circuit, fabricated in 90nm CMOS process, consumes 14 mW from a 1.2 V supply, and only occupies 0.21 × 0.26 mm2.

ABSTRACT ii
摘要 iii
CONTENTS v
LIST OF FIGURES vii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 Basic Concepts and Broadband Techniques of Equalizer 3
2.1 Overview of WireLine Communication 3
2.2 Basic Concepts of Equalizer 5
2.2.1 NRZ and RZ Signaling 5
2.2.2 Pseudo-Random Binary Sequences (PRBSs) 6
2.2.3 Intersymbol Interference 7
2.2.4 Eye Diagram 9
2.2.5 Jitter 11
2.3 Broadband Techniques of Equalizer 12
2.3.1 Capacitive/Resistive Degeneration 12
2.3.2 Inductive Peaking 13
2.3.3 Cherry-Hooper Amplifier 14
Chapter 3 A 20-Gb/s Miniaturized Analog Equalizer Using Folded Active Inductors in 90nm CMOS 17
3.1 Design of Active Inductor 17
3.1.1 Conventional Active Inductors 17
3.1.2 Folded Active Inductor 18
3.2 Circuit Topology 20
3.2.1 Equalizing Filter 20
3.2.2 Predriver 23
3.2.3 Output Buffer 24
3.3 Measurement Results 25
3.3.1 Die Photograph 25
3.3.2 Measurement Setup 25
3.3.3 Eye Diagram 27
3.3.4 Frequency Response 32
3.3.5 Performance Summary 33
Chapter 4 A 20-Gb/s Miniaturized CMOS Analog Equalizer Using 3D Solenoid Inductors in 90nm CMOS 34
4.1 Design of 3D Inductor 34
4.1.1 Basic Concepts of Spiral Inductors 34
4.1.2 3D Stacked Inductors 36
4.1.3 3D Solenoid Inductors 37
4.2 Circuit Topology 41
4.3 Simulation Results 46
4.3.1 Layout 46
4.3.2 Eye Diagram 47
4.3.3 Frequency Response 48
4.3.4 Performance Summary 49
Chapter 5 Conclusion 50
5.1 Conclusion 50
References 51

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