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研究生:王子嵩
研究生(外文):Wang, ZIh-Song
論文名稱:自我對準淺溝絕緣層的NAND快閃記憶體之可靠度研究
論文名稱(外文):The Reliability Study of Self-Aligned Shallow Trench Isolation NAND Flash Memory
指導教授:林崇榮
學位類別:博士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:230
中文關鍵詞:NAND快閃記憶體可靠度自我對準淺溝絕緣層
外文關鍵詞:NAND FlashReliabilitySA-STI
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在過去十年間,由於人們對於容量的需求所以NAND Flash記憶體的尺寸持續地從130奈米微縮到1X奈米。隨著尺寸不斷的微縮,許多微縮的挑戰與新的問題都將接踵而至。因此由於物性與電性微縮限制,微縮傳統懸浮閘極型的NAND Flash 記憶體的工程變得越來越困難與挑戰。本論文將針對這些微縮的問題提出相關可行的設計理念與製造方法,並且在50奈米的NAND Flash技術平台上實現。首先我們對於傳統的NAND Flash記憶胞結構 (自我對準型淺溝槽絕緣層) 提出一種改良型的製程方式。並且針對多次讀寫造成的電性可靠度問題與空間越來越小不夠控制閘填入兩個鄰近的懸浮閘的物性問題,提出相對應的設計方法與製程方式讓尺寸可以持續地微縮下去。因此根據本文提出的改良型的 ”下層平坦型自我對準型淺溝槽絕緣層” 可以有效的克服眼前的微縮問題,並且繼續在50奈米以下的世代被採用。此外,我們也提出了一個新的重大微縮問題在傳統的NAND Flash記憶胞結構上。在本文中把此新的不預期現象命名為”轉向的寫入閘極間絕緣層漏電流”,而且此流電流將會導致許多重大問題 (比如劣化閘極絕緣層與記憶體寫入時間變長)。因此我們針對此微縮瓶頸提出一些相關的記憶胞製程設計概念,比如降低來自控制閘極的側向電場與特殊的閘極間絕緣層工程處理都可以有效的抑制此漏電流的產生。接著本論文也有著眼於懸浮閘極資料保存的能力做一些深入的討論與提出相對應的理論模型,當多晶矽氧化層必須隨著尺寸微縮而變得更薄。為了要解決 ”懸浮閘極電子漏電” 與 “被捕捉電子回灌” 問題,本論文提出懸浮閘表面氮化處理的製程方式。此方式可以有效地解決與改善上述的問題,讓多晶矽氧化層可以隨著尺寸微縮而繼續變得更薄。最後本論有針對來自於最後的鈍化處理造成的NAND Flash記憶體可靠度劣化現象,提出相對應的模型與解決方法。水氣擴散是本文提出的相關理論,並且此模型可以解釋所有可靠度劣化的問題。為了要抑制水氣擴散到NAND Flash 記憶胞,合適的金屬後熱退火製成順序與方式均有在本論文中揭露。根據此後段金屬與鈍化製成方法,我們可以獲得更佳的NAND Flash記憶體耐久度與資料保存能力。總結,本文提出了許多微縮上的製程設計概念與相對應的解決方式。因此根據這些解決方案可以讓NAND Flash記憶體保有相同的可靠度而能持續微縮下去,讓NAND Flash記憶體的容量可以符合現在人們的渴望。
Over the past 10 years, the dimension of NAND flash cell has decreased dramatically, from 130nm to middle-1Xnm. As technology nodes advance, various scaling barriers appear, and minor effects become increasingly problematic. Therefore, scaling conventional floating gate technology is very difficult due to physical and electrical limitations. This dissertation proposes some feasibility of fabricating optimized processes on 50-nm NAND Flash technology. First, a flat-bottom Control Gate (CG) with a raised STI has been developed to maintain adequate reliability distance against stresses from cycling, as well as filling in the small Floating Gate (FG) to FG spacing. Thus, the proposed flat-bottom CG structure and process are the most promising solution for advanced Self-Aligned shallow trench isolation (SA-STI) structure exceeding 50 nm. Second, the “redirection programming electron” Inter-Poly Dielectric (IPD) leakage in the traditional SA-STI structure presented here for the first time and redirection IPD leakage current are determined, these should be considered new phenomena. The design of NAND Flash structure should be optimized by a smaller CG fringing E-field effect and special IPD engineering for this unanticipated leakage current when scaling future NAND Flash. Third, this dissertation demonstrates the feasibility of the degradation model of data retention on NAND Flash memory as the bottom poly oxide (BPO) is scaled down. The proposed solution, involving an optimized IPD film scheme with FG top nitridation, solves the “FG charge loss” problem and eliminates “trapped electrons back-tunneling” from the IPD. Finally, the degradation model of the passivation process on a FG type NAND Flash memory is demonstrated. The water (moisture) diffusion model explains all degradation phenomena and observations explain why post metallization anneal (PMA) should be arranged before the deposition of the top P-SiN or the coating of the top metal with Polymide (PI). This dissertation contributes significantly to efforts to improve the endurance and retention of FG-type NAND Flash memory by optimizing the passivation process flow and film scheme. In summary, this dissertation provides some design considerations for cell structure and promising solutions to continue miniaturizing the technology with the same reliability characteristics.


Chapter 1 Introduction
1.1 Introduction of Non-Volatile Memory
1.2 Development of NAND Flash Memory
1.3 The Operation of NAND Flash Memory
1.4 Fabrication Process of Traditional NAND Flash Memory
1.5 Dissertation Organization

Chapter 2 Review of NAND Flash Memories and Scaling Challenges
2.1 Fabrication Process of Advanced NAND Flash Memory
2.1.1 Self-Aligned Double Patterning
2.1.2 NAND String Formation
2.1.3 Revised Self Aligned STI
2.2 Scaling Challenge of NAND Flash Memory
2.2.1 Physical Limitation
2.2.1.a Self-Aligned Double Patterning
2.2.1.b Challenge in Word Line Direction
2.2.1.c Challenge in Bit Line Direction
2.2.2 Electrical Limitation
2.2.2.a Challenge in Word Line Direction
I. Cell to Cell Interference
II. Direct Channel Interference
III. Negative Vth Shift Program Disturb
IV. Deeper STI Recess Effect
V. Higher Corner E-Field form FG or CG Corner 2.2.2.b Challenge in Bit Line Direction
I. WL to WL Interference (Air Gap Influence)
II. Program Interference
III. FG Induced Barrier Enhancement
IV. Source and Drain IMP Engineering
2.3 Summary
2.3.1 Tow Major Challenges
2.3.2 Planar FG with High-K Inter-Poly Dielectric
2.3.3 3D NAND Flash Memory


Chapter 3 The Optimization of Advanced NAND Flash Memory Fabrication for Reliability Consideration
3.1 Front End Process: STI and Gate Engineering
3.1.1 The Influence of the Deeper STI Recess in SA-STI structure
3.1.1.a The Benefit of the Deeper STI Recess in SA-STI Structure
3.1.1.b Sample Fabrication for STI Recess Influence
3.1.1.c The Verification Method for the Influence of STI Recess Amount

3.1.2 The Phenomenon of Ballistic Current in NAND Flash device
3.1.2.a The Re-directional Program Current in NAND Flash Memory
3.1.2.b Sample Fabrication for the Re-directional Program Current
3.1.2.c The Test Sequence for Model Verification

3.1.3 The Requirement of Inter-Poly Dielectric in NAND Flash Memory
3.1.3.a Main Benefit of NONON Inter-Poly Dielectric Film Scheme
3.1.3.b Sample Fabrication for the Investigation of FG Top Nitridation
3.1.3.c The Test Sequence and Method by 8M Mini-Array

3.2 Backend of Line Process
3.2.1 Improvement Reliability from Optimized BEOL Process
3.2.2 Introduction and Motive of Passivation Impacts of NAND Flash
3.2.3 Sample Fabrication
3.2.4 Impact of Passivation Layers on NAND Flash Memory 3.2.5 Test Sequence and Method for Model Verification

Chapter 4 The Optimization of Front End Fabrication for Reliability Consideration
4.1 The Characteristic Results of STI Recess Investigation in SA-STI Process
4.1.1 The Pre-P/E Cycling Performance: PGM and ERS Characteristics
4.1.2 The Post-P/E Cycling Performance: Non-Uniformity FN Stress Model
4.1.3 Reliability Characteristics: Retention and Endurance
4.1.4 Summary

4.2 The Characteristic Results of Re-directional PGM Current in NAND Flash
4.2.1 Model Verification Description
4.2.2 Model Verification by Difference Temperature
4.2.3 Model Verification by CG Fringing E-field Effect
4.2.4 Model Verification by IPD Barrier Effect
4.2.5 Summary

4.3 The Scaling Limitation of Bottom Oxide in Inter-Poly Dielectric
4.3.1 The Phenomenon of Floating Gate Charge Loss (Before P/E Cycling)
4.3.2 The Phenomenon of Electron Back Tunneling (After P/E Cycling)
4.3.3 The Proposed Solution: FG Top Nitridation process
4.3.4 Summary

Chapter 5 The Optimization of Backend Fabrication for Reliability Consideration
5.1 Confirmation Tunneling Oxide Degradation by Testkey
5.2 The Verification of Stress Model
5.3 The Verification of Hydrogen Model
5.4 The Verification of Moisture Model
5.5 Summary

Chapter 6 Conclusion and Future Work
6.1 Conclusion
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