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研究生:詹欽棟
研究生(外文):Chan, Chin-Tung
論文名稱:互補式金氧半導體之功率結合功率放大器之研製
論文名稱(外文):Design of RF CMOS Power Amplifiers using Power Combining Approach
指導教授:徐碩鴻
指導教授(外文):Hsu, Shuo-Hung
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:106
中文關鍵詞:金氧半場效電晶體功率放大器K頻帶W頻帶微波單晶積體電路
外文關鍵詞:CMOSPower amplifierK-bandW-bandMonolithic microwave integrated circuit (MMIC)
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摘要
本論文的目的是設計並且實現了四個利用金氧半導體場效電晶體(CMOS)製程之放大器。此論文分為三個部分,第一個部分在於介紹功率放大器的基本原理,以及設計考量和一些常見技巧。
在第二部分,我們設計四個應用於24GHz之系統的功率放大器使用了低功率90奈米CMOS製程。第一顆功率放大器採用了高效率的變壓器為了得到更高的功率附加效率。此功率放大器測量得在25GHz飽和輸出功率為15.2 dBm,輸出功率1-dB功率壓縮點(P_1dB)為10.7dBm,功率附加效率為17.4%和線性增益為 10.3 dB且面積為0.975×0.71〖mm〗^2。第二顆功率放大器利用了覆晶技術來增加功率放大器的散熱。此功率放大器在模擬中,飽和輸出功率為13.4 dBm, 輸出功率1-dB功率壓縮點(P_1dB)為11.3 dBm,功率附加效率為12.7%和線性增益為 10.3 dB且面積為0.82×0.71〖 mm〗^2。最後,第三顆K頻段功率放大器,採用了自動調整偏壓技術。從模擬來看,靜態時候的功耗為367mW而其在出功率1-dB功率壓縮點(P_1dB)時功率附加效率為20.5%。此功率放大器在24GHz模擬時可得到飽和輸出功率為22.3 dBm, 輸出功率1-dB功率壓縮點(P_1dB)為20.5 dBm,功率附加效率為24.9%和線性增益為 23.4 dB且面積為1×0.74〖mm〗^2.
在第三部分,此W頻帶功率放大器使用了低功率90nmCMOS製程,由量測可知在頻率為77 GHz時,其飽和輸出功率為13.2 dBm,輸出功率1-dB功率壓縮點(P_1dB)為7.6 dBm,功率附加效率為2.4%和線性增益為 4.1 dB。而晶片總面積只有0.63×0.5 〖mm〗^2.
這些電路顯示了相當吻合的模擬與量測結果,這四顆功率放大器的線性度或效率優於大部分目前相近頻帶已發表的金氧半場效電晶體(CMOS)功率放大器。


Abstract
The goal of the thesis is to design and implement RF power amplifiers in CMOS technology. The thesis consists of three parts. The first part introduces the basics of power amplifier theories and some common design techniques. In the second part, three power amplifiers (PAs) are designed for 24-GHz systems and implemented in a LP 90-nm CMOS technology. The first PA adopts high efficient transformers to improve maximum power-added-efficiency (PAE). This PA achieves a measured saturated output power (P_sat) of 15.2 dBm, an output 1-dB compression point (P_1dB) of 10.7 dBm, a power-added-efficieny (PAE) of 17.4%, and a linear gain of 10.5 dB at 25 GHz, with a chip size of 0.975 × 0.71 〖mm〗^2. The second PA utilizes flip-chip configuration to assist heat dissipation. This PA achieves a simulated P_sat of 13.4 dBm, a P_1dB of 11.3 dBm, a PAE of 12.7%, and a linear gain of 10.3 dB at 24 GHz, with a chip size of 0.82 × 0.71 〖mm〗^2. Finally, the third K-band PA with the proposed adaptive-bias technique is fabricated. According to the simulation, the proposed PA consumes 367 mW at quiescent state and offers 20.5% PAE at the P_1dB. The PA achieves a simulated P_sat of 22.3 dBm, a P_1dB of 20.5 dBm, a PAE of 24.9%, and a linear gain of 23.4 dB at 24 GHz with the chip size of 1 × 0.74 〖mm〗^2.
In the third part, a 77-GHz PA is implemented in a LP 90-nm CMOS technology. The PA achieves a measured P_sat of 13.2 dBm, a P_1dB of 7.6 dBm, a PAE of 2.4% , and a linear gain of 2.4 dB at 77 GHz. The chip size is only 0.63 × 0.5 〖mm〗^2 including all of the testing pads. The simulation results agrees well with the measurement results for the PAs. In addition, all of the PAs demonstrate high performance compared with the prior arts of the CMOS PAs operating at the frequencies at 24 GHz and 77 GHz.
Index Terms –CMOS, Power amplifier, K-band, W-band, RF amplifier, Monolithic microwave integrated circuit (MMIC).

CONTENTS iv
LIST OF FIGURES vii
LIST OF TABLES xii
Chapter I Introduction 1
1.1 Background and Motivation 1
1.2 Literature Survey 3
1.3 Thesis Organization 4
Chapter II Overview of Power Amplifier 5
2.1 Introduction 5
2.2 Important Parameters 6
2.2.1 Output Power 6
2.2.2 Efficiency 7
2.2.3 Linearity 9
2.3 Classification of Power Amplifier 17
2.4 Design techniques of PA 23
Chapter III Design of a High Efficient K-band PA in 90nm CMOS 36
3.1 Introduction 36
3.2 Design of High Efficient Power Amplifier 37
3.2.1 Deep N-well 37
3.2.2 Transformer Design 39
3.3 Proposed Circuitry 41
3.4 Measurement Results 45
3.4.1 Small-Signal Measurements 45
3.4.2 Large-Signal Measurements 49
Chapter IV Design of a Flip-chip Power Amplifier in 90nm CMOS 54
4.1 Introduction 54
4.2 Design of Flip-Chip Power Amplifier 55
4.3 Proposed Circuitry 57
4.4 Simulation Results 60
4.4.1 Layout implementation 60
4.4.2 Small-Signal Simulation 62
4.4.3 Large-Signal Simulation 64
4.5 Measurement Results 66
Chapter V Design of an Adaptive-Biasing Power Amplifier in 90 nm CMOS 69
5.1 Introduction 69
5.2 Design of Adaptive-Bias Power Amplifier 71
5.3 Proposed PA with Adaptive Bias 76
5.4 Simulation Results 78
5.4.1 Small-Signal Simulation Results 79
5.4.2 Large-Signal Simulation 80
Chapter VI Design of a W-Band Power Amplifier using Combining in 90 nm CMOS 84
6.1 Introduction 84
6.2 Design of a W-Band Compact Power Amplifier 85
6.2.1 RC Stabilization Network 85
6.2.2 GCPW Line with Patterned Ground Shield 87
6.3 Proposed Circuit topology 90
6.4 Measurement Results 91
6.4.1 Chip micrograph 91
6.4.2 Small Signal S-parameters 93
6.4.3 Large-Signal Performance 96
Chapter VII Conclusion and Future Work 99
References 101

CONTENTS iv
LIST OF FIGURES vii
LIST OF TABLES xii
Chapter I Introduction 1
1.1 Background and Motivation 1
1.2 Literature Survey 3
1.3 Thesis Organization 4
Chapter II Overview of Power Amplifier 5
2.1 Introduction 5
2.2 Important Parameters 6
2.2.1 Output Power 6
2.2.2 Efficiency 7
2.2.3 Linearity 9
2.3 Classification of Power Amplifier 17
2.4 Design techniques of PA 23
Chapter III Design of a High Efficient K-band PA in 90nm CMOS 36
3.1 Introduction 36
3.2 Design of High Efficient Power Amplifier 37
3.2.1 Deep N-well 37
3.2.2 Transformer Design 39
3.3 Proposed Circuitry 41
3.4 Measurement Results 45
3.4.1 Small-Signal Measurements 45
3.4.2 Large-Signal Measurements 49
Chapter IV Design of a Flip-chip Power Amplifier in 90nm CMOS 54
4.1 Introduction 54
4.2 Design of Flip-Chip Power Amplifier 55
4.3 Proposed Circuitry 57
4.4 Simulation Results 60
4.4.1 Layout implementation 60
4.4.2 Small-Signal Simulation 62
4.4.3 Large-Signal Simulation 64
4.5 Measurement Results 66
Chapter V Design of an Adaptive-Biasing Power Amplifier in 90 nm CMOS 69
5.1 Introduction 69
5.2 Design of Adaptive-Bias Power Amplifier 71
5.3 Proposed PA with Adaptive Bias 76
5.4 Simulation Results 78
5.4.1 Small-Signal Simulation Results 79
5.4.2 Large-Signal Simulation 80
Chapter VI Design of a W-Band Power Amplifier using Combining in 90 nm CMOS 84
6.1 Introduction 84
6.2 Design of a W-Band Compact Power Amplifier 85
6.2.1 RC Stabilization Network 85
6.2.2 GCPW Line with Patterned Ground Shield 87
6.3 Proposed Circuit topology 90
6.4 Measurement Results 91
6.4.1 Chip micrograph 91
6.4.2 Small Signal S-parameters 93
6.4.3 Large-Signal Performance 96
Chapter VII Conclusion and Future Work 99
References 101

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