臺灣博碩士論文加值系統

設計並製作出一個Cross-point記憶體開關來整合於RRAM中，由於記憶體發展的趨勢為高密度、低耗能，而控制電晶體(一般來說是MOSFET)當需要減少元件的大小的時候將面臨問題，平面MOSFET的問題將妨礙記憶體的發展，因此考慮將平面結構發展成三維堆積的結構。
在製程上為求與RRAM上有最佳之相容性，傳統電晶體因製成溫度高，可能導致記憶體之良率下降，故選擇低溫製程之MIM結構並製作出元件,在目前製作出的元件能量測的，且MIM在VON在4V情況下，面積下最大寫入電流Iwrite電流密度約可達，且在絕緣層SiN厚度下在Sneak Path Leakage Effect中電流在寫入電壓Vwrite和Vwrite/2的比值已經達到，且MIM1比值可達，在實際的整合上，寄生電阻扣除後電流在Sneak Path Leakage Effect的比值會更高，目前已把NPN結構與RRAM記憶體結合，未來目標與MIM整合將可提高此二極體的功能性及實用性，可成為未來高密度之3D非揮發性記憶體之控制單元。

In this project, we will design and fabricate a switch for cross-point RRAM applications, since the trend of the development for non-volatile memory is high density, low power consumption. The select devices have the issue for high density memory due to planar structure such as MOSFET. Therefore, the 3D structure will be a candidate for next generation NVM.
In the process, in order to have the best compatibility with RRAM, because of traditional transistors made of high temperature, the yield may lead to memory decline, so choose low-temperature process of MIM structure and produce components. The minimum size for our technology node with devices realized. And in the case of Von in the maximum Ion current density in the areacan up to, and the thickness of the insulating SiN layer the ratio of Vwrite current and Vwrite/2 current has reached, MIM1 device can reach 103. In the actual integration, after allowing for the parasitic resistance in the Sneak Path Leakage Effect current ratio will be higher. We Integrate NPN structure with RRAM to array is working now, and our future work is that integrate NPN structure with RRAM to higher the usability, we look for the high functionality and density for the 3D non-volatile memory with this select device

Publication List I
中文摘要 II
英文摘要 III
致謝 IV
目錄 V
圖目錄 VII
表目錄 XII
第一章 緒論
1-1 記憶體概況 1
1-2 Cross-point記憶體開關選擇器 3
1-3 Cross-point 1S1R 之整合 7
第二章 MIM與MSM元件應用與討論
2-1元件操作原理說明 10
2-2裝置的設計與生產過程與機台介紹 11
2-2-1 MIM/MSM device without ILD passivation 11
2-2-2 MIM device with ILD passivation 15
2-3常溫下的穩定性量測 19
2-4元件電性分析與討論 20
2-4-1 MIM without ILD passivation之電性結果 20
2-4-2 MIM with ILD passivation之電性結果 32
2-5 MSM電性結果 40
第三章 雙向二極體在Interlayer Dielectric (ILD) passivation下的電性討論及與電阻式記憶體之整合
3-1前言 48
3-2常溫下之電性量測與討論 49
3-3變溫下之電性量測與討論 59
第四章 結論與未來研究發展
4-1各章研究總結 63
4-1-1第二章之研究討論 63
4-1-2第三章之研究討論 69
4.2未來工作 71
參考文獻 78

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