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研究生:林彥宇
研究生(外文):Yan-Yu Lin
論文名稱:具有可適性遠端串音消除之4Gbps平行介面接收器
論文名稱(外文):4Gbps Parallel Interface Receivers with Adaptive Far-End Crosstalk Cancellation
指導教授:劉深淵
口試委員:郭泰豪汪重光楊清淵林宗賢
口試日期:2013-01-28
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:60
中文關鍵詞:可適性遠端串音消除平行介面接收器
外文關鍵詞:AdaptiveFar-End Crosstalk CancellationParallel Interface Receivers
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在高速介面中,為了節省印刷電路板之佈局面積和增加資料頻寬,平行之微帶線彼此之間通常擺放得很近。不幸地,這將造成較大的串音雜訊。產生在接收端的串音雜訊稱之為遠端串音。這將造成串音引起的資料抖動以及惡化位元錯誤率。
在本論文中,主要有四個部份。研究動機和論文組成在第一章作介紹。在第二章中,提出使用一個功率偵測迴路達到具有可適性遠端串音消除之4-Gb/s平行介面接收器。利用RC高通濾波器對資料作微分來產生串音消除訊號。此串音消除訊號藉由電流模式加法器來消掉遠端串音訊號。對於不同的通道間距,利用一個功率偵測迴路來偵測剩餘之遠端串音訊號並達到自動調整串音消除訊號之振幅,使得遠端串音訊號被消到最小。
然而,為了正確地消除遠端串音訊號,串音消除訊號和遠端串音訊號兩者的的脈波寬度及振幅要有很好地匹配。在第三章中,提出使用脈波寬度及振幅校正達到具有可適性遠端串音消除之4-Gb/s平行介面接收器。利用可調的RC高通濾波器對資料作微分來產生串音消除訊號。首先,串音消除訊號的脈波寬度藉由一個寬度校正電路使其脈波寬度自動地被校正與遠端串音訊號之寬度相當。然後再由一個振幅校正電路自動地調整串音消除訊號的振幅使得遠端串音訊號被消到最小。同樣地,對於不同的通道間距具有可適性。最後,結論和未來工作在第四章陳述。


To reduce the PCB layout area and increase the data bandwidth, parallel microstrip lines are often closely placed in high-speed interface. Unfortunately, it usually results in larger crosstalk noise. The crosstalk noise induced at the receiver end is called far-end crosstalk (FEXT). It results in the crosstalk-induced jitter (CIJ) and degrades the bit-error rate (BER).
In this thesis, there are mainly four parts. In chapter 1, the research motivation and the organization of thesis are introduced. In chapter 2, 4-Gb/s parallel receivers with adaptive far-end crosstalk cancellation by a power detection loop are presented. The RC high-pass filter is used to differentiate the data to generate the XTC signal. The XTC signal is used to cancel the FEXT signal by using the current-mode adder. A power detection loop is adopted to detect the residual FEXT signal and automatically adjust the amplitude of the XTC signal to minimum the FEXT noise for different channel spacing.
However, to cancel the FEXT signal correctly, both the pulse-widths and amplitudes for the XTC and FEXT signals should be well matched. In chapter 3, 4-Gb/s parallel receivers with adaptive FEXT cancellation by pulse-width and amplitude calibrations are presented. The tunable RC high-pass filter is used to differentiate the data to generate the XTC signal. First, the pulse-width of the XTC signal is automatically adjusted to be close to the FEXT one by using a width calibration circuit. Then the amplitude of the XTC signal is automatically adjusted to minimize the FEXT signal by using an amplitude calibration circuit. Similarly, it achieves the adaptation to different channel spacing. Finally, the conclusion and future work are given in chapter 4.


1. Introduction 9
1.1 Motivation 9
1.1.1 Problems 9
1.1.2 Previous Solutions and The Goal of Research 11
1.2 Organization of Thesis 12
2. 4-Gb/s Parallel Receivers with Adaptive Far-End Crosstalk Cancellation by
A Power Detection Loop 13
2.1 Channel Modeling 14
2.2 Principle of FEXT Cancellation 15
2.3 Adaptive FEXT Cancellation Method 15
2.4 Differentiator and Power Detector 16
2.4.1 Differentiator 16
2.4.2 Power Detector 18
2.5 Proposed Receivers with Adaptive XTC 19
2.5.1 Overall System Architecture 19
2.5.2 Receiver with XTC 22
2.5.3 Comparator 25
2.6 Experimental Results 26
2.7 Performance Summary 32
3. 4-Gb/s Parallel Receivers with Adaptive FEXT Cancellation by Pulse-Width
and Amplitude Calibrations 33
3.1 Principle of FEXT Cancellation 34
3.2 Adaptive FEXT Cancellation Method 35
3.2.1 Concept of Pulse-Width Calibration 35
3.2.2 Concept of Amplitude Calibration 36
3.3 Digitally-controlled HPF and Power Detector 37
3.3.1 Digitally-controlled HPF 37
3.3.2 Power Detector 37
3.4 Proposed Receivers with Adaptive XTC 38
3.4.1 Overall System Architecture 38
3.4.2 Receiver with XTC 40
3.4.3 Pulse-Width Calibration Circuit 43
3.4.4 Amplitude Calibration Circuit 45
3.4.5 Adaptation Time 48
3.5 Experimental Results 49
3.6 Performance Summary and Comparison 55
4. Conclusion and Future Work 57
4.1 Conclusion 57
4.2 Future Work 58
Bibliography 59


[1]J. F. Buckwalter and A. Hajimiri, “Cancellation of crosstalk-induced jitter,” IEEE J. Solid-State Circuits, vol. 41, no.3, pp.621–632, Mar. 2006.
[2]H.-K. Jung, K. Lee, J.-S. Kim, J.-J. Lee, J.-Y. Sim, and H.-J. Park, “A 4 Gb/s 3-bit parallel transmitter with the crosstalk-induced jitter compensation using TX data timing control,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 2891–2900, Nov. 2009.
[3]K.-I. Oh, L.-S. Kim, K.-I. Park, Y.-H. Jun, J. S. Choi, and K. Kim, “A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme,” IEEE J. Solid-State Circuits, vol. 44, no.8, pp.2222–2232, Aug. 2009.
[4]H.-K. Jung, S.-M. Lee, J.-Y. Sim, and H.-J. Park, “A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2010.
[5]K.-J. Sham, M. R. Ahmadi, S. B. G. Talbot and R. Harjani, “FEXT crosstalk cancellation for high-speed serial link design,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2006, pp. 405–408.
[6]T. Oh and R. Harjani, “A 6-Gb/s MIMO crosstalk cancellation scheme for high-speed I/Os,” IEEE J. Solid-State Circuits, vol. 46, no.8, pp.1843–1856, Aug. 2011.
[7]T. Oh and R. Harjani, “4x12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS,” in Proc. Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2012, pp. 140-141.

[8]S.-K Lee, H. Ha, H.-J. Park, and J.-Y. Sim, “A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 140-141.
[9] J. Lee, “A 20Gb/s adaptive equalizer in 0.13-μm CMOS technology”, IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2058-2066, Sep., 2006.
[10]Y.-M. Ying and S.-I. Liu, “A 20Gb/s digitally adaptive equalizer/DFE with blind sampling,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 444-446.
[11]C. S. Taillefer and G. W. Roberts, “Delta-sigma A/D conversion via time-mode signal processing,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 1908-1920, Sept. 2009.


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