臺灣博碩士論文加值系統

本論文呈獻一個基於壓控震盪器的三階連續時間三角積分調變器。以壓控震盪器為基礎的量化器具有開迴路一階雜訊調變以及閉迴路天生動態加權平均等好處，但是輸入電壓對輸出頻率的非線性仍然是個必須解決的問題。這篇論文提出了一個平移平均的方法來延展線性操作區間，並且將調變器中的前饋加法器以及迴路延遲補償皆整合至壓控震盪器當中，節省了額外的硬體並減少消耗功率。本晶片使用台積電六十五奈米互補式金氧半製程所實現，在十六億赫茲的取樣頻率下操作，並於兩千萬赫茲的有效頻寬下得到65.2 dB的訊號雜訊失真比以75.4 dB的訊號無雜散比。在1.2伏特的電源供應下總共消耗21.1毫瓦，所佔晶片面積只有0.159平方毫米。

This thesis presents a third-order continuous-time delta-sigma modulator with a VCO-based quantizer. A VCO-based quantizer possesses attractive characters of open-loop first-order noise-shaping and barrel-shifting output code when used as closed-loop. However, the non-linear nature of the voltage-to-frequency tuning curve is still a problem to be solved. A shifted-averaging linearization technique is proposed and a modulator with the proposed technique is fabricated in TSMC N65 GP+ 1P6M technology. Aside from the linearization technique, the feed-forward voltage summer and excess loop delay compensation are both integrated into the VCO quantizer, which saves power and area. The prototype modulator is operated at 1.6GHz sampling clock. It achieves peak SNDR of 65.2dB and peak SFDR of 75.4dB within 20MHz bandwidth. The chip dissipates 21.1mW from a 1.2V supply. The active area of this modulator occupies only 0.159mm2.

摘要 i
Abstract ii
Contents iii
List of Figures vii
List of Tables xi
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 Fundamentals of Delta-Sigma ADCs 3
2.1 ADC Performance Metrics 3
2.1.1 Signal-to-Noise Ratio (SNR) 3
2.1.2 Signal-to-Noise-and-Distortion Ratio (SNDR) 5
2.1.3 Effective Number-of-Bits (ENOB) 5
2.1.4 Spurious-Free Dynamic Range (SFDR) 5
2.1.5 Figure of Merit (FoM) 6
2.2 Introduction to Delta-Sigma Modulators 7
2.3 DT-CT Modulator Equivalence 9
2.4 Excess Loop Delay 11
2.5 Fundamental of VCO-Based ADCs 13
2.5.1 Introduction to VCO quantizer 14
2.5.2 Prior Arts 15
Chapter 3 Behavioral Simulation of VCO-Based Delta-Sigma Modulators 19
3.1 Introduction 19
3.2 Proposed Shifted-Averaging Technique 19
3.2.1 Shifted-Averaging of VCOs 19
3.2.2 Shifted-Averaging VCO within Delta-Sigma Loop 21
3.2.3 Shift Prediction 22
3.3 Systematic Design of Loopfilter 24
3.4 Clock Jitter 27
3.5 Opamp Non Ideality 29
3.5.1 Opamp Finite Gain-Bandwidth 30
3.5.2 Opamp Slewing Rate 31
3.6 DAC Mismatch and Finite Impedance 31
3.6.1 DAC Mismatch 31
3.6.2 DAC Finite Impedance 34
3.7 VCO Quantizer Frequency Response 35
3.8 Passive Element Process Drift 36
3.9 Summary 38
Chapter 4 Circuit Implementation of Shifted-Averaging VCO Modulator 39
4.1 Introduction 39
4.2 Modulator Architecture 39
4.3 VCO Qauntizer 40
4.4 Analog Core 43
4.4.1 Main DAC 43
4.4.2 Opamp Integrators 48
4.4.3 Clock Buffer 54
4.5 Digital Core 54
4.6 Buffer Core 56
4.7 Layout Considerations 56
4.8 Post-Layout Simulation 58
4.9 Summary 58
Chapter 5 Experimental Results 59
5.1 Introduction 59
5.2 Print Circuit Board Design 59
5.3 Measurement Setup 60
5.4 Measurement Results 61
5.5 Summary 65
5.6 Conclusions 67
5.7 Future Works 67
Bibliography 71

[1]M. Park, A 4th Order Continuous-Time ΔΣ ADC with VCO-Based Integrator and Quantizer, PhD thesis, 2009.
[2]Scott D. Kulchycki, Continuous-Time Sigma-Delta ADCs, http://www.ti.com/lit/an/snaa098/snaa098.pdf
[3]M. Z. Straayer and M. H. Perrott, “A 12-bit, 10-MHz Bandwidth, Continuous-Time ΔΣ ADC with a 5-bit, 950-MS/s VCO-based Quantizer,”IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814, Apr. 2008.
[4]M. Park and M. Perrott, “A 0.13 μm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based Integrator and Quantizer,” in IEEE Int. Solid-State Circuits Conf., 2009, pp. 170–171.
[5]G. Taylor and I. Galton, “A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC,” IEEE J. Solid-State Circuits, vol.45, pp. 2634–2646, Dec. 2010.
[6]K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, and P. Hanu-molu, “A 16mw 78dB-SNDR 10MHz-BW CT-ΔΣ ADC Using Residue-Cancelling VCO-Based Quantizer," IEEE Int. Solid-State Circuits Conf., 2012, pp. 152-154.
[7]B. Razavi, Principles of Data Conversion System Design, Wiley-IEEE Press, New York, 1995.
[8]R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters. New York: Wiley-IEEE Press, 2004.
[9]Gao, W., Shoaei, O., Snelgrove, W.M., “Excess Loop Delay Effects in Continuous-Time Delta-Sigma Modulators and the Compensation Solution,” Proc. IEEE Int. Sym. Circuits Syst. 1, pp. 65-68, June 1997.
[10]S. Yan and E. Sanchez-Sinencio, “A Continuous-Time Modulator With 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth,” IEEE J. Solid-State Circuits, vol.39, no.1, pp. 75–86, Jan 2004.
[11]G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, “A 20 mW 640-MHz CMOS Continuous-Time Sigma-Delta ADC with 20-MHz Signal Bandwidth, 80-dB Dynamic Range, and 12-bit ENOB,” IEEE J. Solid-State Circuits, vol.41, no.12, pp. 2641–2649, Dec 2006.
[12]M. Hovin, A. Olsen, T. Sverre, and C. Toumazou, “Delta-Sigma Modulators Using Frequency-Modulated Intermediate Values,” IEEE J. Solid-State Circuits, vol.32, no.1, pp. 13–22, Jan 1997.
[13]S. Z. Asl, S. Saxena, P. Hanumolu, K. Mayaram, and T. S. Fiez, “A 77 dB SNDR, 4 MHz MASH Modulator with a Second-Stage Multi-Rate VCO-based Quantizer,” Proc. IEEE Custom Integr. Circuits Conf., 2011, pp. 1–4.
[14]J. Daniels, W. Dehaene, M. Steyaert, and A. Wiesbauer, ”A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion,” IEEE Trans. Circuits and Systems I: Regular Papers, Vol.57, No.9, pp. 2404 - 2412, Sept. 2010.
[15]R. Schreier. Delta Sigma Toolbox. http://www.mathworks.com/.
[16]M. H. Perrott. CppSim System Simulator. http://www.cppsim.com.
[17]J. Silva et al., “Wideband Low-Distortion Delta-Sigma ADC Topology,” Electron. Lett., vol. 37, pp. 737–738, Jun. 2001.
[18]J. A. Cherry and W. M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion. Boston, MA: Kluwer, 2000.
[19]Ortmanns, M., Gerfers, F., Manoli, Y., “A Continuous-Time Sigma-Delta Modulator with Reduced Sensitivity to Clock Jitter Through SCR-Feedback,” IEEE Trans. Circuits Syst. I, vol.52, no.5, pp. 875–884, May 2005.
[20]Y.-C. Chang, W.-H. Chiu, C.-C. Lin, and T.-H. Lin, "A 4MHz BW 69dB SNDR Continuous-Time Delta-Sigma Modulator with Reduced Sensitivity to Clock Jitter," IEEE A-SSCC, Nov. 2011, pp. 265-268.
[21]A. G. M. Strollo, D. De Caro, E. Napoli, and N. Petra, “A Novel High Speed Sense-Amplifier-Based Flip-Fop,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 11, pp. 1266–1274, Nov. 2005.
[22]M. Ortmanns, F. Gerfers, “Continuous-Time Sigma-Delta A/D Conversion,” Springer Berlin Heidelberg, 2006.