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研究生:游岳華
研究生(外文):Yueh-Hua Yu
論文名稱:使用校正技巧於電荷泵與頻寬的CMOS寬頻鎖相迴路
論文名稱(外文):CMOS Wideband PLLs with Charge-Pump and Bandwidth Calibration
指導教授:陳怡然陳怡然引用關係
指導教授(外文):Yi-Jan Emery Chen
口試委員:劉深淵蘇朝琴陳伯奇鄭國興李洪松
口試委員(外文):Shen-Iuan LiuChau-Chin SuPoki ChenKuo-Hsing ChengHung-Sung Li
口試日期:2013-05-22
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:124
中文關鍵詞:互補式金氧半導體鎖相迴路頻率合成器寬頻電荷泵校正頻寬校正
外文關鍵詞:CMOSPLLFrequency SynthesizerWidebandCharge-pump CalibrationBandwidth Calibration
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本論文提出了採用0.18微米和90奈米CMOS互補式金氧半導體製程的低突波寬頻鎖相迴路,電荷泵電流校準技術使得鎖相迴路在寬頻率範圍內保持恆定的迴路頻寬,並實現較低的參考突波。第一級電荷泵電流校準和機制與自動頻帶跳頻控制整合一起,校正迴路頻寬同時確保足夠的負電導提供電壓控制的振盪器在整個頻率範圍內發揮作用。第二級電荷泵電流校準電荷泵電流不匹配與脈衝寬度的縮放技術相結合。CMOS 0.18微米PLL操作在4.7-6.1GHz,參考突波低於68.5分貝,在1MHz偏移情況下相位雜訊為-116dBc/Hz。CMOS 90 奈米PLL操作在39.5-47.1GHz,參考突波低於57.6分貝,在1MHz偏移情況下相位雜訊為-92.35dBc/Hz。

This thesis presents a 0.18-μm and a 90-nm CMOS wideband phase-locked loops with low reference spurs. A charge-pump current calibration technique is proposed to maintain a constant loop bandwidth for wide operation frequency range and achieve low reference spurs. First level charge-pump current calibration is seamlessly incorporated in the automatic frequency band hopping control and the mechanism also ensures enough negative transconductance for the voltage-controlled oscillator to function throughout the whole frequency range. The charge-pump mismatch is calibrated by second level charge-pump current calibration combined with a pulse-width scaling technique. The proposed CMOS 0.18-μm PLL operation frequency range covers from 4.7 GHz to 6.1GHz. The measured phase noise is -116 dBc/Hz at 1MHz offset and the reference spur is -68.5 dBc. The proposed CMOS 90-nm PLL operates form 39.5-47.1GHz. The reference spur is below -57.6dB. The measured phase noise is -92.35dBc/Hz at 1MHz offset.

口試委員會審定書 i
誌謝 iii
摘要 iv
ABSTRACT v
CONTENTS vi
LIST OF FIGURES viii
LIST OF TABLES xiii
PUBLICATION LIST xiv
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Contribution of Dissertation 3
Chapter 2 PLL Architecture and Principle 5
2.1 Classification of Phase-Locked Loop 5
2.2 Phase-Locked Loop Circuit Architecture 6
2.2.1 Phase / Frequency Detector 8
2.2.2 Charge-Pump 16
2.2.3 Loop Filter 17
2.2.4 Divider 20
2.2.5 Voltage Controlled Oscillator 26
2.3 The Linear Model of a PLL 32
2.4 Performance Indicators of a PLL 40
2.4.1 Phase Noise 40
2.4.2 Spurs 41
Chapter 3 Bandwidth Calibration 45
3.1 Bandwidth of a PLL 45
3.2 Bandwidth Calibration Techniques 51
3.2.1 Linearization by Flash ADC 51
3.2.2 Linearization by Differential Amplifier 52
3.2.3 Linearization by Square Resonant Frequency 53
3.2.4 Linearization by Direct Control 56
Chapter 4 Charge-pump Current Mismatch Calibration 59
4.1 Current mismatch and spurs of a PLL 59
4.2 Spur Supression Technique 62
4.2.1 Low KVCO 62
4.2.2 High Reference Frequency 64
4.2.3 Low Ripple Voltage 66
4.2.3.1 OP-Amps 66
4.2.3.2 Delay-sampled 67
4.2.3.3 Current Mismatch Calibration 69
Chapter 5 Circuit Design 75
5.1 CMOS 0.18-μm PLL Architecture 75
5.2 CMOS 90-nm PLL Architecture 94
Chapter 6 Experimental Result 105
6.1 CMOS 0.18-μm PLL Experimental Result 105
6.2 CMOS 90-nm PLL Experimental Result 112
Chapter 7 Conclusion 117
REFERENCE 119


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