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研究生(外文):Shih-Jan Luo
論文名稱(外文):The Investigation of Interface Trap of Ge Based Passivation Layer and the Loss Analysis of Through Silicon Via Structure
指導教授(外文):Chee Wee Liu
口試委員(外文):Kuei-Shu Chang-LiaoShoou-Jinn ChangHorng-Chih Lin
外文關鍵詞:GermaniumInterface Trap DensityConductance MethodC-V HysteresisThrough Silicon ViaInsertion Loss
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近代半導體工業跟隨著摩爾定律的規則,持續地將元件微縮進化。但傳統的矽金氧半場效電晶體(MOSFETs)技術已經逐漸面對其微縮的極限。為了要持續維持著元件微縮的步調,必須要開發更高載子遷移率(Carrier Mobility)的新材料來取代傳統矽做為元件通道材料,像鍺或是其他三五族材料目前受到相當的矚目,而其中鍺更是被認為能在未來使用於22奈米節點製程以取代矽。然而,鍺元件仍然存在著許多難題需要克服,其中主要的是高介電係數材料(High-k)的製程整合、表面鈍化的處理以及降低源極/汲極的寄生電阻。
論文中,在(100)、(110)以及(111)的鍺基板上利用高速熱氧化法(RTO)來成長二氧化鍺(GeO2)做為鍺與高介電係數材料的介面層(Interfacial Layer),接著使用了低溫原子沉積(ALD)來生長三氧化二鋁(Al2O3)以保護並增進二氧化鍺的品質,可獲得良好的電容特性。由於鍺的能帶寬度較小,其介面抓陷密度(Interface Trap Density)的擷取必須在低溫下使用電導方法(Conductance Method)量測。並且由SRH model可得知不同溫度下介面抓陷反應之能階。量測結果證明在同樣的製程下的表面抓陷密度:(111)<(100)~(110),與成長厚度:(111)<(100)~(110)大約一致,即成長的速率越慢,其表面抓陷密度越小。另外,低等效氧化層厚度(Low EOT)金氧半元件是一直以來半導體產業追求的目標,我們利用較高介電係數的二氧化鋯(ZrO2)成功的將等效氧化層厚度降低至約0.39奈米等級,並比較得知經過遠距電漿處理(Remote Plasma Treatment)製程後之試片可達到較小介面抓陷密度。
為了遵循摩爾定律,不同於將電晶體的尺寸不停的縮小,取而代之的方法主要有從結構上改變成三維結構,例如鰭式場效應電晶體,又或者是將封裝的方式改成三維堆疊,例如矽晶穿孔技術,如此以來便可以在相同的面積上,增加更多的效能。由於3-D的電路整合包含減少接線長度、降低傳輸時間、縮小系統尺寸等優點,因此論文的另一個主軸為矽晶穿孔(TSV)的電路模型。我們利用電磁模擬軟體:高頻結構模擬(High Frequency Structure Simulation)不同參數條件下的矽晶穿孔插入損耗(Insertion Loss)及訊號耦合(Noise coupling)並利用等效電路模型探討、分析。

Recently, semiconductor industry technology has followed the path of scaling trend based on Moore''s Law. But conventional bulk Si MOSFETs is approaching its fundamental scaling limits. For the continuation of the scaling trend, high mobility materials have been comprehensively investigated as channel material for replacing Si, such as Ge or III-V material due to its high intrinsic carrier mobility. Ge has become a promising candidate to be used on 22nm nodes for beyond CMOS technology, because it has high electron and hole mobility on bulk substrate. At the same time, there are several critical issues for Ge device. The primary challenges to achieve high mobility Ge MOSFETs are the high-k integration process, the improvement of n-type dopants activation, reduction of interface trap density, and proper strain configuration.
In this thesis, using rapid thermal oxidation to grow germanium dioxide on (100), (110) and (111) germanium substrates as interfacial layer between substrate and high-k layer, then use atomic layer deposition to grow aluminum oxide to protect and improve the quality of germanium dioxide which has a good C-V performance. Since the smaller band gap of germanium, the extraction of interface trap density has to use low temperature conductance method. By SRH model, the energy level of interface trap at different temperature can be calculated. The interface trap density of samples on different orientation which is under the same process shows that: (111)<(100)~(110), and the thickness: (111) <(100) ~(110) is on the same trend i.e. the slower the growth rate is, the lower interface trap density will be. In addition, the low EOT MOS devices have always been the goal in semiconductor industry, we use ZrO2 which has higher dielectric constant to successfully reduce the EOT of MOS devices to about 0.39 nanometer level, and the interface trap density can be further decreased by remote plasma treatment process.
To follow Moore''s Law, we scaled down the transistor in the past. But there are still some other technologies to solve the problem, one is three-dimensional structure such as finFET, and another is three-dimensional package such as TSV. Using TSV can increase much more performance in an area on a chip. 3-D package contains reducing the wiring length, reducing transmission time, reducing system size and so on. Therefore, another topic in the thesis is TSV circuit model. We use electromagnetic simulation tool:High Frequency Structure Simulation (HFSS) to simulate the insertion loss and the noise transfer function of TSV under different conditions and analyze the results by equivalent circuit model.

口試委員會審定書 #
致謝 #
Related Publications(相關論文發表) i
摘要 ii
Abstract iv
Contents vi
List of Figures ix
List of Tables xiii
Chapter 1 Introduction
1.1 Background and motivation 1
1.2 Thesis organization 5
Reference 6
Chapter 2 Interface trap characterization of GeO2/Ge and ZrO2/Ge by low temperature conductance method
2.1 Introduction 7
2.2 Theory of conductance method 8
2.3 High mobility channel material : Ge 14
2.4 Characterization of Interface Traps in Ge by Low-Temperature Conductance Technique 16
2.4.1 Sample fabrication: Al/Al2O3/GeO2/p-Ge MISCAPs 16
2.4.2 Sample fabrication: TiN/ZrO2/p-Ge MISCAPs 20
2.4.3 Low-Temperature Conductance Measurements for Full Mapping of Dit 23
2.4.4 Measurement Results and Discussion 25
2.5 Summary 27
Reference 28
Chapter 3 Loss analysis of through silicon via structure
3.1 Introduction 33
3.1.1 Advantages of 3D IC technology over 2D SoC 34
3.1.2 TSV process 38
3.1.3 Problem description 39
3.2 Electromagnetic simulation and equivalent RLC circuit modeling of TSV 40
3.3 Model verification 48
3.3.1 Dielectric loss 48
3.3.2 Metal loss 52
3.4 Summary 53
Reference 54
Chapter 4 Noise Coupling between TSVs
4.1 Introduction 56
4.2 TSV shielding structures for TSV-TSV coupling suppression-p+ guard ring 57
4.3 TSV shielding structures for TSV-TSV coupling suppression-n+/N-well guard ring 67
4.4 Summary 70
Reference 71
Chapter 5 Summary and Future Work
5.1 Summary 72
5.2 Future Works 74
Reference 75

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