(34.229.64.28) 您好!臺灣時間:2021/05/06 06:17
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:宋東鴻
研究生(外文):Tung-Hung Sung
論文名稱:適用於電力線通訊系統之十位元高速管線式類比數位轉換器
論文名稱(外文):Design of 10 bits High Speed Pipelined ADC for Power-Line Communication System
指導教授:陳中平陳中平引用關係
指導教授(外文):Chung-Ping Chen
口試委員:李泰成盧奕璋張順志
口試委員(外文):Tai-Cheng LeeYi-Chang LuSoon-Jyh Chang
口試日期:2013-06-05
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:108
中文關鍵詞:電力線通訊系統管線式類比數位轉換器1.5位元架構放大器分享動態範圍加倍
外文關鍵詞:power-line communicationpipelined ADC1.5-bit per stageOP-amp sharingdynamic range doubling
相關次數:
  • 被引用被引用:0
  • 點閱點閱:144
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
由於高速低功率的特性,管線式類比數位轉換器目前被廣泛地運用在中高解析度的現代通訊系統裡。在本論文中我們藉由台積電90奈米的製程實現了兩個高速的十位元管線式類比數位轉換器。兩顆晶片分別使用了1.5位元和2.5位元的架構來實現;並且運用了放大器分享以及動態輸入範圍加倍的技術降低了功率消耗。其中1.5位元架構的類比數位轉換器另外被整合在我們電力線通訊系統的類比前端電路的晶片當中。
在200MS/s的取樣頻率下,對於1MHz的輸入頻率第一顆類比數位轉換器晶片的SNDR、SFDR和ENOB分別是43.52 dB、55.01 dB以及6.94位元;在180MS/s的取樣頻率下,對於1MHz的輸入頻率第二顆類比數位轉換器晶片的SNDR、SFDR和ENOB分別是35.06 dB、45.34 dB以及5.53位元。另外功率消耗跟FoM的部分,第一顆晶片的功率消耗為51.2毫瓦,FoM為2.08 pJ/convstep;第二顆晶片的功率消耗為37.2毫瓦;FoM為4.47 pJ/convstep。


Pipelined ADC is widely used in modern communication system owing to the fact that it has the characteristic of low power, mid-high resolution and high speed. In this thesis, we propose two different architectures of 10 bits 200MS/s pipelined ADC. In the first ADC, 1.5-bit architecture is used. To reduce the power consumption, two techniques, OP-amp sharing and dynamic range doubling (DRD) are applied in this ADC. Moreover, this ADC is also applied in another chip: the analog front-end of the power-line communication system. In the second ADC, 2.5-bit architecture is used and we merge the sample and hold circuit and the 1st MDAC circuit into one stage by using OP-amp sharing. Besides, DRD technique is also applied in this ADC. Both these two chips are fabricated in TSMC 90nm process.
As for measurement results, with the 1MHz input frequency and the 200MS/s sampling rate, the SNDR, SFDR and ENOB of the first ADC are 43.52 dB, 55.01 and 6.94 bits respectively. Besides, with the 1MHz input frequency and the 180MS/s sampling rate, the SNDR, SFDR and ENOB of the second ADC are 35.06 dB, 45.34 dB and 5.53 bits respectively. In addition, the power consumption and the FoM of the first ADC are 51.2mW and 2.08 pJ/convstep; the power consumption and the FoM of the second ADC are 37.2mW and 4.47 pJ/convstep.


口試委員會審定書 #
誌謝 i
中文摘要 iii
ABSTRACT v
CONTENTS vii
LIST OF FIGURES xii
LIST OF TABLES xvii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Power-Line Communication System 1
1.2.1 HomePlug 2
1.2.2 Analog Front-End (AFE) of PLC 3
1.3 Thesis Organization 4
1.4 Contribution of This Thesis 5
Chapter 2 Fundamental of Pipelined ADC 7
2.1 Introduction 7
2.2 ADC Performance Metrics 7
2.2.1 Differential Nonlinearity (DNL) 7
2.2.2 Integral Nonlinearity (INL) 8
2.2.3 Signal to Noise Ratio (SNR) 9
2.2.4 Signal to Noise and Distortion Ratio (SNDR) 10
2.2.5 Resolution and Effective Number of Bits (ENOB) 10
2.2.6 Spurious Free Dynamic Range (SFDR) 10
2.2.7 Figure of Merit (FoM) 11
2.3 Architectures of Pipelined ADC 11
2.3.1 Conventional Pipelined ADC 11
2.3.2 General 1.5-bit per stage 10 bits Pipelined ADC 13
2.3.3 General 2.5 bits per stage 10 bits Pipelined ADC 16
Chapter 3 The Proposed Two 1.5-bit and 2.5-bit Pipelined ADCs with DRD and Op-amp Sharing techniques 19
3.1 Introduction 19
3.2 Building Blocks of Pipelined ADC 19
3.2.1 Sample and Hold Amplifier (SHA) Circuit 19
3.2.2 Multiplying Digital to Analog Converter (MDAC) 21
3.3 OP-amp Sharing Technique 23
3.4 Dynamic Range Doubling (DRD) Technique 26
3.5 Proposed 10 bits Pipelined ADCs with DRD and Op-amp Sharing techniques 31
3.5.1 1.5-bit architecture with DRD and OP-amp Sharing 31
3.5.2 Delay Element and Digital Error Correction (DEC) of 1.5-bit Pipelined ADC 32
3.5.3 2.5-bit architecture merged SHA with 1st MDAC with OP-amp Sharing and DRD 34
3.5.4 Delay Element and Digital Error Correction (DEC) of 2.5-bit Pipelined ADC 35
Chapter 4 Circuit Implementation and Simulation Results 37
4.1 Introduction 37
4.2 Circuit Implementation of the First Work 37
4.2.1 Front-End SHA Circuit and Bootstrapped Switch 37
4.2.2 1.5-bit Sharing Stage and DRD-Modification 39
4.2.3 Enhanced Switch Circuit 41
4.2.4 Two Stages Folded-Cascode Operational Amplifier 42
4.2.5 Common Mode Feedback (CMFB) Circuit and Bias Circuit of OP-amp 46
4.2.6 1.5-bit Sub-ADC and DAC 49
4.2.7 Capacitance-Divided Dynamic Comparator 50
4.2.8 Clock Generator of the First Work 52
4.3 Circuit Implementation of the Second Work 54
4.3.1 Merged SHA and 1st DRD-Modification 1.5-bit MDAC 55
4.3.2 2.5-bit Sharing Stage 56
4.3.3 Two Stages Gain-Boosting Operational Amplifier 57
4.3.4 2.5-bit Sub-ADC and DAC 60
4.3.5 Clock Generator of the Second Work 61
4.4 Whole Chip Post-Layout Simulation Results 63
4.4.1 Simulation Results of the First Work 63
4.4.2 Simulation Results of the Second Work 66
4.5 Summary 70
Chapter 5 Experimental Results and Performance Discussion 71
5.1 Introduction 71
5.2 Measurement Environment setup 71
5.3 Die Photos and PCB Layout 72
5.4 Measurement Results 74
5.4.1 Measurement Results of the First Work 74
5.4.2 Measurement Results of the Second Work 79
5.5 Performance Discussion 83
5.5.1 Clock Skew of the Multi-Clock-Generators 83
5.5.2 Dummy Capacitances in Layout Alignment 86
5.6 Summary 88
Chapter 6 Analog Front-End of the PLC System 91
6.1 Introduction 91
6.2 The AFE Circuit of the PLC System 91
6.3 Measurement Result 93
6.3.1 Measurement Result of the Receiver 93
6.3.2 Measurement Result of the Transmitter and the Receive 96
6.4 Another Work of the Receiver for PLC system 98
6.5 Summary 102
Chapter 7 Conclusion and Future Work 103
7.1 Conclusions 103
7.2 Future work 104
Reference 105


[1]HomePlug (n.d.). Retrieved April 2, 2013, from
http://en.wikipedia.org/wiki/HomePlug
[2]K. Findlater, T. Bailey, A. Bofill, “A 90nm CMOS Dual-Channel Powerline Communication AFE for Homeplug AV with a Gb Extension,” IEEE International Solid-State Circuit Conference, pp. 464-466, Feb. 2008.
[3]B. Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, 1995
[4]Dong Young Chang, “Design Techniques for a pipelined ADC without using a front-end sample-and-hold amplifier,” IEEE transactions on Circuits and System I: Regular papers, pp. 2123-2132, Nov. 2004.
[5]S. Sutarja and P. R. Gray, “A pipelined 13-bit 250-ks/s 5V analog-to-digital converter,” IEEE J. Solid-State Circuits, vol.23, pp.1316-1323, Dec.1988.
[6]B. Razavi, Design of Analog CMOS Integrated Circuits, McGRAW-Hill, 2001.
[7]Byung-Moo Min and Peter Kim, “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol.38, no. 12, pp.1316-1323, Dec.2003.
[8]K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, “A 250mW 8b 52M sample/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifier,” IEEE J. Solid-State Circuits, vol.32, no. 3, pp.312-320, Mar.1997.
[9]O. Stroeble, V. Dias, C. Schwoerer, “An 80MHz 10b pipelined ADC with dynamic range doubling and dynamic reference selection,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech Papers, pp. 462-539, Feb. 2004.
[10]S. Jiang, M. Anh Do, “An 8-bit 200-Msample/s pipelined ADC with mixed-mode front-end S/H circuit,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 1430-1440, July 2008.
[11]Byung-Geun Lee, Byung-Moo Min, Gabriele Manganaro, Jonathan W. Valvano, “A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC,” IEEE J. Solid-State Circuits, vol. 43, no. 12 pp. 2613-2619, Dec. 2008.
[12]A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May 1999.
[13]D. W. Cline and P. R. Gray, “A Power Optimized 13-b 5-Msample/s Pipelined Analog-to-Digital Converter in 1.2μm CMOS,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 294-303, Mar. 1996.
[14]O. Choksi and L. R. Carley, “Analysis of switched-capacitor common-mode feedback circuit,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no.12, pp. 906-917, Dec. 2003.
[15]K. Bult and G.J.G.M. Geelen, “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain,” IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1379-1384, Dec 1990.
[16]L. Sumanen, M. Waltari and K. A. I. Halonen, “A 10-bit 200-MS/s COMS Parallel Pipeline A/D Converter,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1048-1055, Jul. 2001.
[17]S. T. Ryu, B. S. Song and K. Bacrania, “A 10-bit 50-MS/s pipelined ADC With Opamp Current Reuse,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 475-485, Mar. 2007.
[18]O. Stroble, V. Dias and C. Schwoerer, “An 80MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection,” IEEE International Solid-State Circuit Conference, pp. 462-539, Feb. 2004.
[19]S. Jaing, A. V. Do, K. S. Yeo and W. M. Lim, “An 8-bit 200MSampke/s Pipelined ADC With Mixed-Mode Front-end S/H,” IEEE Trans. Circuits Syst. I, vol. 55, no. 6, Jul. 2008.
[20]B. G. Lee and R. M. Tsang, “A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-gm Opamp,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 883-890, Mar. 2009.
[21]G. Geelen, E. Paulus and D. Simanjuntak, “A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC with 0.5pJ/Conversion-step,” IEEE International Solid-State Circuit Conference, pp. 782-791, Feb. 2006.
[22]S. C. Lee, Y. D. Jeon, J. K. Kwon and Kim, “A 10-bit 205-MS/s 1.0-mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp.2688-2695, Dec. 2007.
[23]G. Geelen, E. Paulus, D. Simanjuntak and H. Pastoor, “A 90nm CMOS 1.2V 10 bits Power and Speed Programmable Pipelined ADC with 0.5pJ/Conversion-step,” IEEE International Solid-State Circuit Conference, pp. 782-791, Feb. 2006.
[24]M. Yoshioka, M. Kudo, T. Mori and S. Tsukamoto, “A 0.8V 10b 80MS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing,” IEEE International Solid-State Circuit Conference, pp. 452-614, Feb. 2007.
[25]Y. Chai and J. T. Wu, “A 5.37-mW 10b 200MS/s Dual-Path Pipelined ADC,” IEEE International Solid-State Circuit Conference, pp. 462-464, Feb. 2011.
[26]Yen-Chuan Huang and Tai-Cheng Lee, “A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique,” IEEE International Solid-State Circuit Conference, pp. 1157-1166, Feb. 2011.


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔