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研究生:凃智展
研究生(外文):Chih-Chan Tu
論文名稱:應用於生醫感測系統之低功率低雜訊類比前端電路設計
論文名稱(外文):Design of Low-Power Low-Noise Analog Front-End Circuits for Biomedical Applications
指導教授:林宗賢林宗賢引用關係
口試委員:黃柏鈞李洪松劉深淵張順志
口試日期:2013-07-17
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:155
中文關鍵詞:低功率低雜訊感測器類比前端電路儀表放大器生醫應用
外文關鍵詞:Low PowerLow NoiseSensorAnalog Front-End CircuitsInstrumentation AmplifierBiomedical Applications
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生理訊號感測在醫學臨床診斷上具有重要意義。以往生理訊號的量測皆須仰賴大型機台,拜科技進步之賜,現今的半導體工業已允許我們將整個系統微小化並實作於一個電路板,甚至是單一晶片上。將整個感測系統包含前端電路,類比數位轉換器,數位訊號處理器以及無線傳輸/接收模組全部整合在一個晶片內,是近幾年國際間熱門的研究課題。本論文著重於探討應用於此系統之類比前端電路設計。此電路必須將極其微弱且低頻的生理信號放大,去除來自外界與電路本身可能的雜訊干擾,同時亦要求低功率以滿足可攜式需求。
本論文實作並量測三個不同架構的晶片。三個架構皆為電容回授式儀表放大器。第一個架構成功量測出心電圖訊號,而未使用動態偏移補償技術的結果,導致電路閃爍雜訊影響了信號的品質。第二個架構在原本的放大器之中利用動態補償技術,以截波之方式達到去除閃爍雜訊的效果。此電路亦包含一個交換電容式低通濾波器以前饋補償的方式來去除因電極不匹配而造成電路失去功能。量測結果顯示電路具有高通濾波的效果,並成功去除電路之閃爍雜訊,然而因交換電容電路產生的雜訊堆疊影響了信號的品質。第三個架構改良於第二個架構,利用混合轉導電容濾波器以及切換電容的方式,在低功率的情況下成功實現了低雜訊。與前兩個架構相比,亦省下更多的電路面積。
此三個電路皆實作於台積電0.18微米製程。第一個晶片核心面積為0.67平方毫米,在1伏特的電源下消耗1.73微安培的電流,並達到14.69的雜訊效率指標(NEF)。第二個晶片核心面積為0.63平方毫米,在1.8伏特下消耗4.2微安培,NEF為 62.06。第三個晶片核心面積為0.42平方毫米,在1.8伏特下消耗2.27微安培,NEF為6.16。


The thesis presents the design of analog front-end circuits for biomedical applications. The analog-front-end circuit is the most critical building block in bio-potential monitoring SoC, since it should amplify very weak signals under noisy aggressors. The solutions to address these problems are described below: First, the front-end instrumentation amplifier should have HPF characteristics to filter out electrode offset. Second, the amplifier should achieve good balancing to resist 60Hz coupling from the mains. Finally, Dynamic Offset Cancelling (DOC) technique is usually used to cancel the effect of amplifier offset and in-band flicker noise.
Three circuit architectures are implemented and the first two are verified, with the third chip under fabrication. All the chips employ capacitively-coupled instrument amplifier topology to achieve high power efficiency. The first chip used the architecture without chopper, and ECG waves are successfully measured. However, it suffers from flicker noise and parasitic capacitor trade-off problems. The second chip is implemented with chopper to get rid of flicker noise, with a ripple-reduction loop to suppress the output ripple caused by modulated offset. A switched-capacitor low-pass filter (SC-LPF) is employed to cancel the system input DC offset from electrode mismatch. The offset voltages and flicker noise are successfully moved out in measurement. However, due to the switching nature, the noise aliasing problem occurs when the SC-LPF is turned on. The Last chip is modified from the second one, instead of using a SC-LPF to cancel the electrode offset, a hybrid gm-C and SC architecture is used both to achieve area efficiency and low noise. The noise aliasing problem is greatly suppressed to the previous one.
The first chip occupies 0.67 mm2 chip area and consumes 1.73-μA current from a 1-V supply. The NEF is 13.6 due to flicker noise problems. The second chip occupies 0.63 mm2 core chip area and consumes 2.1-μA current (4.2-μA with the SC-LPF) from a 1.8-V supply. It achieves a noise efficiency factor (NEF) of 4.29 when SC-LPF is turned off; and 62.06 when SC-LPF is turned on due to noise aliasing. The third chip occupies 0.42 mm2 area, drawing 2.1-μA from 1.8-V supply, and achieves 6.16 NEF with all the functions employed. All the chips are implemented with TSMC 0.18-μm process.


Chapter 1 Introduction 1
1.1 Background 1
1.2 Dissertation Overview 3
Chapter 2 Fundamentals of Analog Front-End Circuits 5
2.1 Fundamentals of Sensor Read-Out Systems 5
2.2 Architectures of AFE circuits 6
2.3 Non-Idealities in Sensor Read-Out Systems 10
2.3.1 Offset Voltage 10
2.3.2 Noise 13
2.3.3 Common-Mode Variations 16
2.4 Dynamic Offset Compensation Techniques 17
2.4.1 Autozeroing 17
2.4.2 Chopping 20
2.5 Summary 23
Chapter 3 Design of a 1-V AFE for ECG Applications 25
3.1 Introduction 25
3.2 Circuit Architecture 25
3.3 Circuit Behavioral Overview 26
3.3.1 Signal Transfer Function 26
3.3.2 Noise Analysis 27
3.3.3 Common-mode Rejection Ratio 31
3.4 Pseudo Resistors 33
3.5 OPAMP Design 37
3.5.1 DC Gain and Bandwidth 37
3.5.2 CMFB Circuits 41
3.5.3 Noise Response 45
3.5.4 Offset 46
3.6 System Level Simulation Results 48
3.6.1 Signal Transfer Function 48
3.6.2 Noise Response 48
3.6.3 CMRR 50
3.7 Measurement Results 52
3.7.1 Chip Pin Configurations 52
3.7.2 PCB Setup 52
3.7.3 DC Measurement 54
3.7.4 Time-Domain ECG Measurement Results 55
3.7.5 AC Response 56
3.7.6 Noise Response 58
3.7.7 CMRR 61
3.8 Summary 62
Chapter 4 Design of AFE for EEG Applications Using Chopped CCIA and Feed-Forward EOV Compensation 65
4.1 Introduction 65
4.2 Prior Art Review 65
4.3 System Behavior Overview 67
4.3.1 Signal Transfer Function 68
4.3.2 Noise 70
4.4 The Behavior Model of OPAMP and RRL 72
4.4.1 Analysis of OPAMP and RRL 72
4.4.2 Offset Ripple Feedback Path through Capacitors 81
4.4.3 Modified RRL Circuit 86
4.4.4 Noise of OPAMP Including RRL 86
4.5 The Behavior Model of Switched-Capacitor LPF 88
4.6 Transistor Level Design and Simulation Results 93
4.6.1 OPAMP Design 93
4.6.2 RRL Design 97
4.6.3 Biasing Resistor 99
4.6.4 SC-LPF 101
4.7 System Simulation Results 103
4.8 Measurement Results 106
4.8.1 Chip Configuration and Measurement Setup 106
4.8.2 Transient Measurement Results 108
4.8.3 AC Measurement Results 110
4.8.4 Noise Measurement Results 112
4.9 Summary and Conclusion 114
Chapter 5 Design of AFE for EEG Applications Using Hybrid gm-C and SC Filter 115
5.1 Introduction 115
5.2 System Architecture 115
5.2.1 System Transfer Function 115
5.2.2 Noise Analysis 118
5.3 Circuit Implementation 119
5.3.1 Behavior Model of DSL 119
5.3.2 Circuit Implementation of DSL 123
5.3.3 Duty Cycle Generator 126
5.4 Simulation Results 128
5.5 Measurement Results 130
5.5.1 Chip Pin Configuration 130
5.5.2 Measurement Setup and PCB 132
5.5.3 AC Measurement Results 133
5.5.4 Noise Measurement Results 134
5.6 Summary 138
Chapter 6 Conclusions and Future Works 141
6.1 Conclusions 141
6.2 Future Work 143
Chapter 7 Appendix: Ideal Models and Simulation Tips 145
7.1 Introductions 145
7.2 Ideal Gm Cell 145
7.3 Ideal Switch 148
7.4 Simulation Tips 149
References 151


[1]R. F. Yazicioglu, C. Van Hoof, and R. Puers, Biopotential Readout Circuits for Portable Acquisition Systems, Springer, 2009.
[2]R. Wu, J. H. Huijsing, and K. A. A. Makinwa, Precision Instrumentation Amplifiers and Read-Out Integrated Circuits, Springer, 2013.
[3]E. Ramsden, Hall-Effect Sensors - Theory and Applications, 2nd Ed., Newnes, 2006.
[4]M.A.P. Pertijs, and W.J. Kindt, "A 140 dB-CMRR Current-Feedback Instrumentation Amplifier Employing Ping-Pong Auto-Zeroing and Chopping," IEEE J. Solid-State Circuits, vol.45, no.10, pp. 2044 - 2056, Oct. 2010.
[5]R. Wu, K.A.A. Makinwa and J.H. Huijsing, “A Chopper Current-Feedback Instrumentation Amplifier with a 1mHz 1/f Noise Corner and an AC-Coupled Ripple Reduction Loop,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3232 - 3243, Dec. 2009.
[6]R. Wu, J.H. Huijsing and K.A.A. Makinwa, “A Current-Feedback Instrumentation Amplifier with a Gain Error Reduction Loop and 0.06% Untrimmed Gain Error,” IEEE J. Solid-State Circuits, vol. 46, no. 12, Dec. 2011.
[7]R. Wu, Y. Chae, J.H. Huijsing, K.A.A. Makinwa, “A 20-b ±40-mV Range Read-Out IC With 50-nV Offset and 0.04% Gain Error for Bridge Transducers” IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2152 - 2163, Sep. 2012.
[8]R.F. Yazicioglu, P. Merken, R. Puers, and C. Van Hoof, “A 60 μW 60 nV/√Hz Readout Front-End for Portable Biopotential Acquisition Systems,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1100 - 1110, May. 2007.
[9]Q. Fan, F. Sebastiano, J.H. Huijsing and K.A.A. Makinwa, “A 1.8μW 1μV-Offset Capacitively-Coupled Chopper Instrumentation Amplifier in 65nm CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1534 - 1543, Jul. 2011.
[10]R. R. Harrison, and C. Charles, “A Low-Power Low-Noise CMOS Amplifier for Neural Recording Applications,” IEEE J. Solid-State Circuits, vol. 38, is. 6, pp. 958 - 965, Jun. 2006.
[11]Q. Fan, J.H. Huijsing and K.A.A. Makinwa, “A Capacitively Coupled Chopper Instrumentation Amplifier With a ±30V Common-Mode Range 160dB CMRR and 5μV Offset,” IEEE ISSCC Dig. Tech. Papers, 2012, pp. 374 – 376.
[12]B. Razavi, Design of Analog CMOS Integrated Circuits, McHrawHill, 2001.
[13]P. G. Drennan, and C. C. McAndrew, "Understanding MOSFET Mismatch for Analog Design," IEEE J. Solid-State Circuits, vol.38, no.3, pp. 450 - 456, Mar. 2003.
[14]W. Liu, X. Jin, J. Chen, M-C. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P.K. Ko and Chenming Hu, “BSIM3v3.2.2 MOSFET Model Users'' Manual”, 1999.
[15]J. F. Witte, K. A. A. Makinwa, and J. H. Huijsing, Dynamic Offset Compensated CMOS Amplifiers, Springer, 2009.
[16]C. C. Enz and G. C. Temes, “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization,“ Proc. IEEE, vol. 84, no. 11, pp. 1584 - 1614, Nov. 1996.
[17]J. F. Witte, K. A. A. Makinwa, and J. H. Huijsing, Dynamic Offset Compensated CMOS Amplifiers, Springer, 2009.
[18]R. Schreier, J. Silva, J. Steensgaard, and G. C. Temes, “Design-Oriented Estimation of Thermal Noise in Switched-Capacitor Circuits,” IEEE Trans. Circuits Syst.-I, vol. 52, no. 11, pp. 2358 - 2367, Nov. 2005.
[19]R. Burt, and J. Zhang, “A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter With Synchronous Integration Inside the Continuous-Time Signal Path," IEEE J. Solid-State Circuits, vol.41, no.12, pp. 2729 - 2736, Dec. 2006.
[20]M. Belloni, E. Bonizzoni, A. Fornasari, and F. Maloberti, “A Micropower Chopper—CDS Operational Amplifier,” IEEE J. Solid-State Circuits, vol.45, no.12, pp. 2521 - 2529, Dec. 2010.
[21]Y. Kusuda, " Auto Correction Feedback for Ripple Suppression in a Chopper Amplifier," IEEE J. Solid-State Circuits, vol.45, no.8, pp. 1436 - 1445, Aug. 2010.
[22]X. D. Zou, X. Y. Xu, L. B. Yao, and Y. Lian, “A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip,” IEEE J. Solid-State Circuits, pp. 1067 - 1077, Apr. 2009.
[23]J. Xu, R. Yazicioglu, B. Grundlehner, P. Harpe, K.A.A. Makinwa and C. Van Hoof, “A 160μW 8-Channel Active Electrode System for EEG Monitoring,” IEEE Trans. on Biomedical Circuits and Systems, vol. 5, no. 6, pp. 555 – 567, Dec. 2011.
[24]N. Verma, .A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A. P. Chandrakasan, “A Micro-Power Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System,” IEEE J. Solid-State Circuits, vol.45, no.4, pp. 804 - 816, Apr. 2010.
[25]T. Denison, K. Consoer, W. Santa, A. -T. Avestruz, J. Cooley, and A. Kelly, “A 2 μW 100 nV/rtHz Chopper-Stabilized Instrumentation Amplifier for Chronic Measurement of Neural Field Potentials,“ IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2934 – 2945, Dec. 2007
[26]K. Nagaraj, ”A Parasitic- Insensitive Area-Efficient Approach to Realizing Very Large Time Constants in Switched- Capacitor Circuits,” IEEE Trans. Circuits Syst., vol.36, no.9, pp. 1210 – 1216, Sep. 1989.
[27]E. Rodriguez-Villegas, A.J. Casson, and P. Corbishley, “A Subhertz Nanopower Low-Pass Filter,” IEEE Trans. Circuits Syst.-II, vol. 58, no. 6, pp. 351 - 355, Jun. 2011.
[28]J. Xu, Q. Fan, J.H. Huijsing, C. Van Hoof, R.F. Yazicioglu, and K.A.A. Makinwa, “Measurement and Analysis of Current Noise in Chopper Amplifiers,” IEEE J. Solid-State Circuits, vol. 48 no. 7, pp. 1575 - 1584, Jul. 2013.
[29]R.F. Yazicioglu, P. Merken, and C. Van Hoof, “A 200μW Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems,” IEEE J. Solid-State Circuits, vol.43, no.12, pp. 3025 - 3038, Dec. 2008.
[30]J. Yoo, L.Yan, D. El-Damak, M.A.B. Altaf, A.H. Shoeb, and A.P. Chandrakasan, “An 8-Channel Scalable EEG Acquisition SoC With Patient-Specific Seizure Classification and Recording Processor,” IEEE J. Solid-State Circuits, vol.48, no.1, pp. 214 - 228, Jan. 2013.
[31]K. Kundert, “Simulating Switched-Capacitor Filters with SpectreRF,” http://www.designers-guide.org/analysis/sc-filters.pdf
[32]R. Schaumann, H. Xiao, and M. E. Van Valkenburg, Analog Filter Design, 2nd ed., Oxford University Press, 2011.
[33]CedanceR, “Virtuoso Spectre Circuit Simulator RF Analysis User Guide,” Product Version 6.2, 2007. http://www.seas.gwu.edu/~vlsi/ece218/SPRING/reference/manual_cadence_spectreRF.pdf
[34]Tian Xia, “Cadance Software Tutorial,” http://www.cems.uvm.edu/~txia/cadence.htm


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