本論文以台積電0.18微米製程，分別設計並實現了使用電感耦合之3Gb/s、6Gb/以及10Gb/s應用於短距非接觸性無線資料連結的三種接收端電路，總功率消耗分別為9mW、15mW以及18mW，分別達到了3pJ/bit、2.5pJ/bit以及2pJ/bit的接收端效率。經由量測結果證實，本系統可以在單端輸出擺幅為250mV時最高達到每秒傳輸八兆位元以上的資料，並且僅有20mW左右的功率消耗。

A wireless data link for short range communcation is implemented by using coupled transmission line.We designed three version of Receiver.They has energy efficiency of 3pJ/bit at 3Gb/s version,2.5pJ/bit at 6Gb/s version and 2pJ/s at 10Gb/s version. The proposed short range wireless link is implemented in TSMC 0.18μm process for demonstration of this architecture and it is proved by the measurment results that the proposed structure can transmit up to 8Gb/s data at output swing of 250mVpeak-to-peak and only consumes 20mW.

第 1 章 簡介 1
1.1 動機 1
1.2 電感耦合收發機 2
1.3 非接觸式短距電感耦合收發機研究現況 3
1.4 各章節簡介 7
第 2 章 研究基礎 8
2.1 簡介 8
2.2 數位訊號的表示方法[10][11] 9
2.3 電路頻寬設計考量 13
2.4 眼圖(Eye Digram) 14
2.5 抖動(Jitter) 16
2.6 位元錯誤率(Bit Error Rate, BER) 18
2.7 隨機雜訊(Random Noise)對位元錯誤率(BER)的影響[10] 19
2.8 其他雜訊對眼圖以及位元錯誤率的影響 22
第 3 章 接收端電路 29
3.1 電感耦合收發機電路 29
3.2 接收端電路 30
3.3 3 Gb/s接收機前端電路 31
3.4 利用Inductive Peaking技巧之10Gb/s接收端電路 37
3.4.1 Inductive Peaking如何提升差動放大器的頻寬[10] 37
3.4.2 電路架構與模擬 39
3.5 6Gb/s無電感接收機電路 44
3.5.1 使用capacitive peaking技巧的寬頻放大器 45
3.5.2 高速遲滯比較器 48
3.5.3 利用主動回授技巧的寬頻放大器[8] 50
第 4 章 量測結果 55
4.1 量測環境 55
4.2 Chip A: 3Gb/s接收機前端電路 57
4.2.1 通道量測 57
4.2.2 接收電路 59
4.2.3 接收端電路與通道 61
4.3 Chip B: 10Gb/s接收端電路 64
4.4 SMA對眼圖的影響以及Offset對電路的影響 67
第 5 章 結論 69
參考文獻 73

[1]Noriyuki Miura, Daisuke Mizogchi, Takayasu Sakurai, and Tadahiro Kuroda, “Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 829-837, July 2005.
[2]Seulki Lee, Jerald Yoo, and Hoi-Jun Yoo, ”A 200-Mbps 0.02-nJ/b dual-mode inductive coupling transceiver for cm-range multimedia application,” IEEE Transactions on Circuit and System-I, vol.56, no. 5, pp.1063-1072, May 2009.
[3]Shusuke Kawai, Hiroki Ishikuro, and Tadahiro Kuroda, "A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card,” in Proc. IEEE ISSCC Dig. Tech. Papers, 2010, pp. 264-265.
[4]Yuxiang Yuan, Andrzej Radecki, Noriyuki Miura, Iori Aikawa,Yasuhiro Take, Hiroki Ishikuro, and Tadahiro Kuroda, ”Simultaneous 6Gb/s data and 10mW power transmission using nested clover coils for non-contact memory card,” Symposium on VLSI Circuit, Jun. 2010, pp.199-200.
[5]Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, and Tadahiro Kurda, ”A 12Gb/s non-contact interface with coupled transmission lines,” in Proc. IEEE ISSCC Dig. Tech. Papers, 2012,pp. 492-494.
[6]Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuit Second Edition, Cambridge University Press, Dec. 22 2004.
[7]Ken’ichiro Hijioka, Masaharu Matsudaira, Koichi Yamaguchi, and Masayuki Mizuno, “A 5.5Gb/s 5mm contactless interface containing a 50Mb/s bidirectional sub-channel employing common-mode OOK signaling,” in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2013, pp. 406-408.
[8]Sherif Galal and Behzad Razavi, "10-Gb/s limiting amplifier and laser/modulator driver in 0.18um CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 38, no.12, pp. 2138-2146, Dec. 2003.
[9]Renuka P. Jindal, ”Gigahertz-band high-gain low-noise AGC amplifier in fine-line NMOS,” IEEE Journal of Solid-State Circuits, vol. SC-22, no. 8, pp. 512-521, Aug. 1987.
[10]Behzad Razavi, Design of Integrated Circuits for Optical Communications, New York: McGraw Hill, 2003.
[11]潘俊, ”應用於3D-IC並使用垂直偶合電感之晶片間的高速無線連結,” 台灣大學電子工程學研究所碩士論文, 台灣大學, 2011.
[12]劉深淵、楊清淵,鎖相迴路, 滄海書局, 1998.
[13]“Jitter fundamentals : Agilent 81250ParBERT jitter injection and analysis capabilities,” http://cp.literature.agilent.com/litweb/pdf/5988-9756EN.pdf.
[14]李瑜, ”應用於晶片間通訊的時脈回復電路及高效率介面電路設計,” 國立中興大學電機工程學系碩士論文, 中興大學, 2005.