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研究生:謝秉均
研究生(外文):Ping-Chun Hsieh
論文名稱:具有嚴格輸出電壓調控與自動波谷切換之一次側控制準諧振返馳式轉換器設計
論文名稱(外文):Design of a Primary-Side-Control Quasi-Resonant Flyback Converter With Tight Output Voltage Regulation and Self-Calibrated Valley Switching
指導教授:陳秋麟陳秋麟引用關係
指導教授(外文):Chern-Lin Chen
口試委員:黃文楠林志毅羅有綱涂榮杰
口試委員(外文):Wen-Nan HuangChih-Yi LinYu-Kang LoRong-Jie Tu
口試日期:2013-06-06
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:94
中文關鍵詞:返馳式轉換器一次側控制輸出電壓調控準諧振波谷切換
外文關鍵詞:flyback converterprimary-side controloutput voltage regulationquasi-resonantvalley switching
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  本篇論文針對一次側控制之準諧振返馳式轉換器提出可達成準確輸出電壓調控之一次側偵測電路與全自動之波谷切換技術。藉由追蹤輔助繞組的電壓斜率,控制晶片可使用簡單的類比電路,在二次側電感之電流降至某一固定值的瞬間取得輸出電壓資訊,進而減少輸入線電壓與輸出負載對於輸出電壓的影響。為了方便以類比方式偵測電壓的斜率值,將輔助繞組的回授電壓與一固定斜率之斜坡電壓相加,使偵測電路改為追蹤零斜率之瞬間。
  本文所提出的自動波谷切換技術採用擾動觀察法來偵測諧振之波谷,不需要任何額外的離散元件即可達成波谷切換。除此之外,為了避免在較輕載時產生嚴重的電磁干擾,採用波谷省略方式來降低切換頻率,使得功率電晶體在第一個之後的汲極電壓波谷開始導通。考慮到電壓偵測接腳存在一定程度的雜散電容而使得諧振波谷點產生延遲,本文也提出可測量與修正RC延遲之電路來校正此非理想效應。
  採用世界先進0.5-um 5-V/40-V CMOS高低壓混合製程之電路模型,本文將所提出之電路技術整合在返馳式轉換器控制晶片中並進行全系統之模擬。針對本文所設計輸出電壓為6.2 V與額定功率5 W之一次側準諧振返馳式轉換器,模擬結果顯示在最高與最低之輸入線電壓下,從10%負載到全載的範圍中輸出電壓之變動量皆不大於0.8%。同時,若針對不同準諧振頻率、負載電流、與雜散電容進行模擬,所提出的波谷切換電路皆可準確使功率電晶體導通在汲極電壓之最低點。


This thesis presents methods and circuits to achieve tight output voltage regulation and self-calibrated valley switching for primary-side-control quasi-resonant (QR) flyback converters. By tracking the slope of auxiliary winding voltage, the controller retrieves the output voltage information at a fixed diode current with a simple analog method, and it thus suppresses the load and line effects on the output voltage. To sense the voltage slope, a compensating ramp is applied to the feedback voltage and the sensing circuit detects the zero-slope point instead.
The proposed self-calibrated valley switching circuit is based on perturb and observe (P&O) algorithm to automatically detect the QR valley, and no extra off-chip component is required. Besides, to avoid EMI problem, the valley skipping method is employed to switch on the power MOSFET at later QR valley rather than the first one to lower switching frequency under light load condition. Considering the valley-point mismatch effect due to parasitic capacitance, RC delay estimation and tangency extraction circuit are also developed to correct the non-ideal effect.
A primary-side flyback controller incorporating the two proposed circuits has been designed and simulated using the SPICE model for VIS 0.5-m 5-V/40-V high-voltage CMOS process. Simulation results from a 6.2-V/5-W QR flyback converter exhibit 0.8% output voltage variation from 10% load to full load considering both low and high line voltages. Meanwhile, simulations conducted under different QR frequencies, various load conditions, and different amounts of parasitic capacitance confirm the validity of the proposed valley switching technique.


謝辭 i
中文摘要 ii
ABSTRACT iii
CONTENTS v
LIST OF FIGURES ix
LIST OF TABLES xiii
Chapter 1 Introduction 1
1.1 Background 1
1.1.1 Operating Principles of a Flyback Converter 3
1.1.2 Typical Functional Blocks of a Flyback Control IC 6
1.1.3 Operational Stages of a Flyback Control IC 9
1.2 Evaluation Metrics 11
1.2.1 Load/Line Regulation: 11
1.2.2 Efficiency 11
1.2.3 Standby Power 12
1.3 Conventional Feedback Scheme of a Flyback Converter 12
1.4 Issues on Hard Switching 14
1.5 Research Objective 15
1.6 Overview 17
Chapter 2 Primary-Side Control and Quasi Resonance in Flyback Converters 20
2.1 Survey of Primary-Side-Control Flyback Converters 20
2.1.1 General Considerations 20
2.1.2 Load Compensation Method 22
2.1.3 Sampling at Zero Diode Current 23
2.1.4 Sampling at Non-Zero Diode Current 23
2.1.5 Sampling at a Constant Non-Zero Diode Current 24
2.2 Soft Switching 25
2.2.1 Load-Resonant Converters 26
2.2.2 Quasi-Resonant Converters 27
2.3 The Challenges of Quasi-resonant Flyback Converter 29
2.3.1 Variation of Resonant Frequency 31
2.3.2 Maximum Switching Frequency and Valley Skipping 31
2.3.3 Gate Driver Delay 32
2.3.4 Parasitic Capacitance at Voltage Sensing Pin 33
2.4 Survey of Quasi-resonant Flyback Converters 34
2.4.1 Zero Current Detection Method 35
2.4.2 Synchronization with RC Delay Network 35
2.4.3 Self-Calibrated Valley Switching 36
Chapter 3 Proposed Primary-Side Sensing Circuit with Tight Output Voltage Regulation 38
3.1 Principle of Primary-Side Sensing 38
3.2 Circuit Implementation 39
3.2.1 Slope Compensation Circuit 39
3.2.2 Zero-Slope Detector 40
3.3 Practical Issue on Primary-Side Sensing 44
3.3.1 Primary-Side Snubber 45
3.3.2 Reduction in Bandwidth of Voltage Buffer 46
3.4 Simulation Results 47
3.5 Summary 48
Chapter 4 Proposed Self-Calibrated Valley Switching Circuit 49
4.1 Principle of Self-Calibrated Valley Switching 49
4.1.1 Perturb and Observe Method in Valley Switching 51
4.1.2 On-Chip Estimation of RC Delay in a Sinusoid 51
4.1.3 Valley-Point-Mismatch Correction Method 53
4.2 Circuit Implementation 54
4.2.1 Interleaved-Sampling Valley Switching Circuit 55
4.2.2 Reduction of Gate-Driver Delay Effect 59
4.2.3 Valley Skipping Technique 60
4.2.4 RC Delay Estimation Circuit 62
4.2.5 QR Tangency Extractor and Compensator 64
4.3 Simulation Results 66
4.4 Summary 69
Chapter 5 Multi-Mode Operation and Full-System Simulation of the Primary-Side-Control Quasi-Resonant Flyback Converter 70
5.1 System Design and Compensation Scheme 70
5.2 Multi-mode Operation 75
5.2.1 Green-Mode Oscillator 75
5.2.2 Burst-Mode Control 76
5.3 Full-system Simulation 78
5.3.1 Performance of Output Voltage Regulation 78
5.3.2 Performance of Valley Switching 81
Chapter 6 Conclusions and Future Works 85
6.1 Conclusions 85
6.2 Obstacles and Future Works 86
6.2.1 Chip Verification and Experiments 86
6.2.2 Temperature Effect on Output Voltage 86
6.2.3 Dummy Load Requirement 87
REFERENCES 89
APPENDIX 93
A.1 Layout of Control IC 93


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