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研究生:蔡松芳
研究生(外文):Sung-Fang Tsai
論文名稱:超高畫質高效能視訊編碼器晶片之演算法及架構設計
論文名稱(外文):Algorithm and Architecture Design of Bandwidth Efficient HEVC Encoder for 8K UHDTV Applications
指導教授:陳良基陳良基引用關係
指導教授(外文):Liang-Gee Chen
口試委員:楊家輝賴永康卜令楷吳安宇陳美娟蔡宗漢簡韶逸
口試委員(外文):Jar-Ferr YangYeong-Kang LaiLin-Kai BuAn-Yeu WuMei-Juan ChenTsung-Han TsaiShao-Yi Chien
口試日期:2013-01-25
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:147
中文關鍵詞:視訊編碼超高畫質高效能視訊編碼編碼器
外文關鍵詞:Video encodingUHDTVH.265HEVCencoderchip
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視訊日益廣泛地運用在各種不同的應用情境中。以網路頻寬而言,預計2014年九成的網際網路頻寬都將用來傳遞視訊信號。為了求得更真實的廣視角體驗,未來視訊解析度的要求也將提升到7680x4320p的超高視覺(SHV)解析度。在此超高解析度下,目前的H.264/AVC視訊壓縮技術將無法提供足夠的壓縮率。次世代的高效能影像壓縮標準(HEVC)將比前一代的H.264/AVC高出52%的壓縮能力,足夠提供4320p的壓縮能力。然而,其對於記憶體頻寬的要求與複雜度均大幅提高,需要有新的硬體架構設計法則。
在本篇論文中,我們提出了一單晶片HEVC視訊編碼器的硬體設計,我們針對記憶體頻寬與複雜度,提出了高複雜度的模式決定演算法,3層記憶體階層架構,以及畫面層級過濾流程。此視訊編碼器最高能提供8192x4320p畫素的即時每秒30張的編碼能力,使用28奈米製程製作,總面積為25mm2 , 8350K等效邏輯閘。比較之前所提出針對H.264設計的系統,在同樣的品質下,我們所提出的系統可節省62%的頻寬。

Video is increasingly used in a wide variety of applications. In the future, more than 90% of internet traffic will be video in 2014. While the bandwidth-consuming video is more and more used, resolution requirement on the other hand is going up to 8K UHDTV/SHV, making bandwidth a serious problem. To support such high resolution video for mass usage, video compression is very important. The next generation standard H.265/HEVC provides more than 50% compression rate compared with H.264/AVC, enabling 4K/8K UHDTV applications. However, the bandwidth and complexity problem of H.265/HEVC at UHDTV poses new challenges to video codec designers. These problem needs to be solved and least amount of quality loss should expose. In this dissertation, we proposed a single-chip bandwidth efficient H.265/HEVC encoder that supports real-time encoding of 8192x4320p at 30fps.
Proposed low-cost high complexity mode decision hardware architecture supports complex prediction modes in H.265/HEVC.
For loop filtering, we proposes some hardware-oriented hardware architecture that supports non-deblocking loop filtering efficiently. In addition, 3-level memory architecture supports huge bandwidth requirement for motion estimation. At system level, bandwidth-efficient frame-level pipeline is proposed and saves extra bandwidth. The proposed system is also implemented in chip. The core size of the chip is 25mm^2 which contains 8350K gates with 7.55MB on-chip SRAM using 28nm CMOS Technology. The coding gain is over 62% above all the previous work, and bandwidth efficiency is also highest.

Abstract xiii
1 Introduction 1
1.1 Trend of Ultra High Resolution Television System . . . . . . . . . 1
1.2 Development of Video Coding Systems and Standards . . . . . . 3
1.3 H.265/High Efficiency Video Coding Overview . . . . . . . . . . 6
1.4 Design Challenges of 8K UHDTV HEVC Encoder . . . . . . . . 12
1.5 Research Contributions . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Dissertation Organization . . . . . . . . . . . . . . . . . . . . . . 15
2 Algorithm and Architecture Design of Prediction Engine in HEVC Encoder 17
2.1 Coding Tree Block Structure . . . . . . . . . . . . . . . . . . . . 17
2.2 Architecture Design of Intra Prediction . . . . . . . . . . . . . . . 19
2.2.1 Intra Prediction in HEVC . . . . . . . . . . . . . . . . . . 19
2.2.2 Design Challenge . . . . . . . . . . . . . . . . . . . . . . 23
2.2.3 HEVC Intra Prediction of Hardware Architecture Design . 23
2.3 Algorithm and Architecture Design of Inter Prediction . . . . . . 27
2.3.1 Inter Prediction in HEVC . . . . . . . . . . . . . . . . . . 27
2.3.2 Design Challenges . . . . . . . . . . . . . . . . . . . . . 30
2.3.3 Dual AMVP-centered parallel IME . . . . . . . . . . . . 32
2.3.4 Interleaving interpolation one-pass FME . . . . . . . . . . 34
2.3.5 Inter Prediction Architecture . . . . . . . . . . . . . . . . 34
2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3 Design of Low-cost High Complexity Mode Decision Hardware 37
3.1 Rate Distortion Optimized Mode Decision and Quantization Process in HEVC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Proposed High Complexity Mode Decision Flow . . . . . . . . . 41
3.3 PU-level Early Mode Decision . . . . . . . . . . . . . . . . . . . 42
3.4 Transform Unit Design . . . . . . . . . . . . . . . . . . . . . . . 43
3.5 Efficient CU-layer High Complexity Mode Decision . . . . . . . 45
3.5.1 Design of SSD Cost Unit . . . . . . . . . . . . . . . . . . 45
3.5.2 Design of Bit Counter . . . . . . . . . . . . . . . . . . . 46
3.6 Mode Decision Pipeline Architecture . . . . . . . . . . . . . . . . 59
3.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4 Analysis and Design of Loop Filters in HEVC 63
4.1 Sample Adaptive Offset . . . . . . . . . . . . . . . . . . . . . . . 64
4.1.1 Algorithm Introduction . . . . . . . . . . . . . . . . . . . 64
4.1.2 SAO Coefficient Accumulation . . . . . . . . . . . . . . 68
4.1.3 Quadtree Decision . . . . . . . . . . . . . . . . . . . . . 68
4.2 Adaptive Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.2 Analysis of ALF Encoding Pass . . . . . . . . . . . . . . 72
4.2.3 Analysis of ALF Classification . . . . . . . . . . . . . . . 76
4.2.4 Analysis of Filter Pattern . . . . . . . . . . . . . . . . . . 78
4.2.5 Content-Adaptive Sub-Sampling for Co-matrices Accumulation . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.2.6 Non-Deblocking Loop Filter Engine . . . . . . . . . . . . 85
4.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5 Bandwidth Efficient Frame-level System Architecture for HEVC Encoder 89
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.2 Proposed Online-filtering Frame-level Pipelining . . . . . . . . . 91
5.2.1 Design Challenge . . . . . . . . . . . . . . . . . . . . . . 91
5.2.2 One-pass SAO/ALF Flow . . . . . . . . . . . . . . . . . 93
5.2.3 Online-filtering SAO/ALF Scheduling . . . . . . . . . . . 95
5.2.4 Slice-Parallel Dual CABAC Engine . . . . . . . . . . . . 98
5.3 2D Pixel Pipelining Architecture for SAO/ALF Filtering . . . . . 100
5.4 3-Level Memory Hierarchy Design . . . . . . . . . . . . . . . . . 106
5.5 Proposed HEVC Encoder . . . . . . . . . . . . . . . . . . . . . . 112
5.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6 HEVC Encoder Chip Implementation for 8K UHDTV Application 117
6.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.2 Chip Implementation and Results Comparison . . . . . . . . . . . 119
7 Conclusion and FutureWork 127
7.1 Principal Contributions . . . . . . . . . . . . . . . . . . . . . . . 127
7.2 Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.2.1 Algorithm Improvement . . . . . . . . . . . . . . . . . . 129
7.2.2 Architecture Exploration . . . . . . . . . . . . . . . . . . 130
7.2.3 Application View . . . . . . . . . . . . . . . . . . . . . . 131
7.2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Bibliography 133

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