臺灣博碩士論文加值系統

本論文提出一個適用於高解析度通訊系統的十位元數位類比轉換器。此數位類比轉換器應用於電力線通訊之類比前端接收發器中的傳送器，並達到電力線網路聯盟之最新規格(HomePlug AV2)。
為了改善靜態表現，本論文使用6 (thermometer-coded)-4 (binary-weighted)分段分時的編碼架構來達到良好匹配同時降低資料轉換時的突波。此外，我們亦使用四象限對稱方式來完成電流源陣列的設計；並加入假電晶體於陣列邊緣，降低位於陣列中心與邊緣之電流源間的誤差。針對動態表現方面，我們使用動態元件匹配技術[7][11][12]來提升線性度。
本晶片使用台積電90奈米互補式金氧半製程，晶片主動區域面積約0.35mm2。數位電路的電壓供應為1.2V，類比電路的電壓供給為1.2-V。最大的積分非線性誤差(INL)為-0.57LSB，最大的微分非線性誤差(DNL)為-0.44LSB。無雜散動態範圍(SFDR)在400MS/s之Nyquist取樣下為45dB。整體功率消耗為25.42mW。

A 10-bit current-steering digital-to-analog converter (DAC) has been proposed for high accuracy communication systems. This chip is used for the transmitter (Tx) of the powerline communication (PLC) analog-front-end (AFE), and it reaches the standard of the HomePlug AV2 (2MHz~86MHz).
In order to improve static performance, we use 6(thermometer-coded)-4 (weighted) segmented decoding architecture to get good matching and reduce the glitch. Furthermore, we implement the current source array as common centroid and adding dummy current sources around the array to reduce the mismatch between edge and center. For dynamic performance consideration, the proposed DAC uses the Dynamic Element Matching (DEM) technique [7][11][12] to achieve good linearity.
The chip was fabricated in TSMC 90 nm CMOS technology and occupied 0.35 mm2 for active area. The supplies for the analog and digital circuits both are 1.2V. The maximum INL and DNL are -0.57 LSB and -0.44 LSB respectively. The SFDR is up to 45 dB for 400MS/s of Nyquist-rate sampling. The power consumption is 25.42mW.

口試委員會審定書 i
誌謝 v
中文摘要 vii
ABSTRACT viii
CONTENTS ix
LIST OF FIGURES xiii
LIST OF TABLES xix
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Powerline Communication System 2
1.3 The Specification of DAC in PLC 3
1.4 Thesis Organization 4
Chapter 2 Fundamental Concepts of Digital-to-Analog Converter 5
2.1 Introduction 5
2.2 DAC Architecture 7
2.2.1 Resistors Sting DAC 7
2.2.2 R-2R-Based DAC 7
2.2.3 Charge Redistribution DAC 8
2.2.4 Current-Steering DAC 10
2.3 DAC performance 12
2.3.1 Static performance 12
2.3.1.1 Resolution 13
2.3.1.2 Offset Error 13
2.3.1.3 Gain Error 14
2.3.1.4 Integral Nonlinearity (INL) 14
2.3.1.5 Differential Nonlinearity (DNL) 15
2.3.2 Dynamic Performance 16
2.3.2.1 Glitch 16
2.3.2.2 Signal-to-Noise Ratio (SNR) 17
2.3.2.3 Signal-to-Noise and Distortion Ratio (SNDR) 17
2.3.2.4 Total Harmonic Distortion (THD) 18
2.3.2.5 Spurious Free Dynamic Range (SFDR) 18
Chapter 3 Implementation of current-steering DAC 19
3.1 Segmented Current-steering DAC 19
3.1.1 Static Performance Improvement 21
3.1.1.1 Segmentation choosing 21
3.1.1.2 6-to-63 Thermometer decoding 22
3.1.1.3 Layout Consideration 26
3.1.2 Dynamic Performance Improvement 28
3.1.2.1 Code-Dependent Switching Transients (CDSTs) 28
3.1.2.2 Code-Dependent Loading Variation (CDLV) 30
3.2 Propose current-steering DAC 33
3.2.1 Dynamic Element Matching (DEM) 33
3.2.2 Matlab Simulation of Current Source Area 34
3.2.3 Circuit Implementation of DEM 38
Chapter 4 Simulation Result 43
4.1 Matlab Simulation 43
4.2 HSpice Simulation 50
4.2.1 Static Performance 50
4.2.2 Dynamic Performance 53
4.2.2.1 Pre-simulation (Fs=400MHz) 53
4.2.2.2 Post-simulation (Fs=400MHz) 54
4.2.2.3 MTPR 55
4.2.3 Simulation Summary 57
Chapter 5 Test Setup and Experimental Result 59
5.1 Die Photo 59
5.2 PCB Design Consideration 60
5.2.1 Static Testing PCB 60
5.2.2 Dynamic Testing PCB 61
5.3 Measurement Setup 63
5.3.1 Static Performance Measurement Setup 63
5.3.2 Dynamic Performance Measurement Setup 64
5.4 Experimental Result 65
5.4.1 Static Performance 65
5.4.2 Dynamic Performance 65
5.4.2.1 FS= 100 MS/s (Fin= 0.5 FS, 0.1 FS, 0.05FS) 66
5.4.2.2 FS= 200 MS/s (Fin= 0.5 FS, 0.1 FS, 0.05FS) 67
5.4.2.3 FS= 400 MS/s (Fin= 0.5 FS, 0.1 FS, 0.05FS) 68
5.4.2.4 Dynamic Measurement summary 69
5.4.3 MTPR Measurement 70
5.4.4 Summary 71
5.4.5 Problems Discussion 72
5.4.5.1 Static performance ( INL and DNL ) 72
5.4.5.2 Dynamic performance ( SFDR ) 72
Chapter 6 Conclusion and Future Work 73
6.1 Conclusion 73
6.2 Future Work 75
Bibliography 77






LIST OF FIGURES
Fig.1 1 PLC system used for digital home application 2
Fig.1 2 Analog front-end (AFE) for Powerline Communication (PLC) 3
Fig.2 1 Block Diagram of a N-bit DAC 5
Fig.2 2 R-string 3-bit DAC 7
Fig.2 3 R-2R based DAC 8
Fig.2 4 Charge redistribution DAC 9
Fig.2 5 Clock Diagram of Charge redistribution DAC 9
Fig.2 6 Diagram of Charge redistribution DAC at Ф1 high 9
Fig.2 7 Diagram of Charge redistribution DAC at Ф2 high 10
Fig.2 8 N-bit binary-weighted current-steering DAC 11
Fig.2 9 N-bit thermometer-coded current-steering DAC 11
Fig.2 10 Offset error 13
Fig.2 11 Gain error 14
Fig.2 12 INL (a)End-point; INL (b)Best-fit 15
Fig.2 13 DNL 15
Fig.2 14 Mid-code transition 17
Fig.3 1 Typical segmented current-steering DAC 19
Fig.3 2 10-bit current-steering DAC for 6-4 segmented diagram 20
Fig.3 3 Normalized required area versus percentage of segmentation 21
Fig.3 4 3-to-7 decoder 22
Fig.3 5 14-to-63 decoder 23
Fig.3 6 (a) Transient error code (b) Time-division improvement 24
Fig.3 7 Time-division decoding block diagram 25
Fig.3 8 (a) DFF (Rising) (b) P latch 25
Fig.3 9 (a) single-to-differential buffer (b) current source driver (Latch) 25
Fig.3 10 common centroid current source array 26
Fig.3 11 Current source array 27
Fig.3 12 Bias circuit (global bias circuit and local bias circuit) 28
Fig.3 13 Layout of current source array 28
Fig.3 14 Nyquist-rate sampling diagram 29
Fig.3 15 Low crossing point of current switching diagram 29
Fig.3 16 (a) ideal current source (b) one current source (c) actual current sources 30
Fig.3 17 Output impedance (a) simple current cell (b) cascoded current cell 31
Fig.3 18 Bode plot (a) Current source Zimp (b) cascoded current source Zimp 31
Fig.3 19 charge injection and clock feedthrough reduction 32
Fig.3 20 Conventional structure 34
Fig.3 21 DEM structure 34
Fig.3 22 INL yield versus relative standard deviation of current source, σI 35
Fig.3 23 Unit current source area vs. relative standard deviation(σ(I)/I) 37
Fig.3 24 Current source area vs. overdrive voltage(VOV) 37
Fig.3 25 Proposed 10-bit current-steering DAC with DEM 38
Fig.3 26 Random Selector (RS) 39
Fig.3 27 9-bit PRNG 40
Fig.3 28 PRNG test in Matlab 40
Fig.3 29 8-bit selector 41
Fig.3 30 7-bit shifter 42
Fig.4 1 Probability density function 43
Fig.4 2 fundamental hybrid architecture 44
Fig.4 3 DEM architecture 44
Fig.4 4 (a) fundamental hybrid architecture; (b) DEM architecture 45
Fig.4 5 (a) fundamental hybrid architecture; (b) DEM architecture 45
Fig.4 6 8.4um2 (a) fundamental hybrid architecture; (b) DEM architecture 46
Fig.4 7 5.25um2 (a) fundamental hybrid architecture; (b) DEM architecture 46
Fig.4 8 3.5um2 (a) fundamental hybrid architecture; (b) DEM architecture 47
Fig.4 9 1.05um2 (a) fundamental hybrid architecture; (b) DEM architecture 47
Fig.4 10 0.525um2 (a) fundamental hybrid architecture; (b) DEM architecture 47
Fig.4 11 SFDR versus Area with different segments 49
Fig.4 12 Pre-simulation of DNL and INL@ TT 51
Fig.4 13 Pre-simulation of DNL and INL@ FF 51
Fig.4 14 Pre-simulation of DNL and INL@ SS 51
Fig.4 15 Post-simulation of DNL and INL@ TT 52
Fig.4 16 Post-simulation of DNL and INL@ FF 52
Fig.4 17 Post-simulation of DNL and INL@ SS 52
Fig.4 18 Fs=400MHz (a)Fin=0.5FS (b)Fin=0.25FS @TT 53
Fig.4 19 Fs=400MHz (a)Fin=0.5FS (b)Fin=0.25FS @FF 53
Fig.4 20 Fs=400MHz (a)Fin=0.5FS (b)Fin=0.25FS @SS 53
Fig.4 21 Fs=400MHz (a)Fin=0.5FS (b)Fin=0.25FS @TT 54
Fig.4 22 Fs=400MHz (a)Fin=0.5FS (b)Fin=0.25FS @FF 54
Fig.4 23 Fs=400MHz (a)Fin=0.5FS (b)Fin=0.25FS @SS 54
Fig.4 24 Fs=400MHz in=0.5Fs @ TT (a) LBondwire=0.5nH (b) LBondwire=1nH 55
Fig.4 25 Home Plug Av2 (Fin=2~86MHz) in Matlab 55
Fig.4 26 Home Plug Av2 (Fin=2~86MHz) in HSpice 56
Fig.4 27 Layout of the proposed DAC 58
Fig.5 1 Die photo 59
Fig.5 2 PCB of static performance testing 60
Fig.5 3 PCB of dynamic performance testing 61
Fig.5 4 Termination of the current-steering DAC 62
Fig.5 5 DAC static performance measurement setup 63
Fig.5 6 Static performance measurement in CIC 63
Fig.5 7 DAC dynamic performance measurement setup 64
Fig.5 8 Dynamic performance measurement in CIC 64
Fig.5 9 Measurement INL and DML 65
Fig.5 10 FS= 100 MS/s, Fin= 0.5Fs (a) Conventional (b) DEM 66
Fig.5 11 FS= 100 MS/s, Fin= 0.1Fs (a) Conventional (b) DEM 66
Fig.5 12 FS= 100 MS/s, Fin= 0.05Fs (a) Conventional (b) DEM 66
Fig.5 13 FS= 200 MS/s, Fin= 0.5Fs (a) Conventional (b) DEM 67
Fig.5 14 FS= 200 MS/s, Fin= 0.1Fs (a) Conventional (b) DEM 67
Fig.5 15 FS= 200 MS/s, Fin= 0.05Fs (a) Conventional (b) DEM 67
Fig.5 16 FS= 400 MS/s, Fin= 0.5Fs (a) Conventional (b) DEM 68
Fig.5 17 FS= 400 MS/s, Fin= 0.1Fs (a) Conventional (b) DEM 68
Fig. 5 18 FS= 400 MS/s, Fin= 0.05Fs (a) Conventional (b) DEM 68
Fig.5 19 SFDR @ Fs=100MHz/s 69
Fig.5 20 SFDR @ Fs=200MHz/s 69
Fig.5 21 SFDR @ Fs=400MHz/s 69
Fig.5 22 HomePlug AV2 MTPR measurement 70



 
LIST OF TABLES
Table.1 1 The specification of DAC in PLC 4
Table.2 1 Function of R-2R based DAC 8
Table.2 2 Comparison between thermometer coded and binary weighted 12
Table.3 1 characteristic polynomial 41
Table.4 1 μ and σ of current source 44
Table.4 2 Segment versus current source size 48
Table.4 3 SFDR versus total area with different Segments 49
Table.4 4 Comparison of pre-simulation and post-simulation 57
Table.4 5 Pad placement 58
Table.5 1 Comparison table 71
Table.6 1 Performance of specification versus this work 73

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