(3.238.96.184) 您好!臺灣時間:2021/05/12 17:17
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:蕭淯方
研究生(外文):Yu-Feng Hsiao
論文名稱:具三維結構之K頻段CMOS變壓器結合式功率放大器與效率改善技術之研究
論文名稱(外文):Research of K-band CMOS Transformer Combined Power Amplifier With 3-D Architecture and Efficiency Enhancement Technique
指導教授:黃天偉
指導教授(外文):Tian-Wei Huang
口試委員:張嘉展蔡政翰
口試日期:2013-06-26
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電信工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:126
中文關鍵詞:功率放大器變壓器結合三維結構高輸出功率放射狀架構Doherty
外文關鍵詞:Power amplifierTransformer combining3-D architectureHigh powerRadial structureDoherty
相關次數:
  • 被引用被引用:0
  • 點閱點閱:183
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
隨著無線通訊的發展,以互補式金氧半場效電晶體製程實現之射頻積體電路逐漸受到市場重視,在收發機中以功率放大器為最關鍵的電路。因此本論文將著重於互補式金氧半場效電晶體功率放大器之設計與分析。
在第二章中,以180奈米金氧半場效電晶體製程實現一個24-GHz超微小面積之功率放大器。為了微小晶片面積的設計,此功率放大器在輸出及輸入端採用變壓器同時實現功率結合、阻抗匹配及單端和差動訊號轉換的功能。透過推挽式的架構在電路對稱中心產生一虛擬接地,直流偏壓可被直接饋入而不需大容值的旁路電容,晶片面積可進一步的縮小。此功率放大器在24-GHz附近頻段達到最小的晶片面積0.26mm2及最高的面積使用效率。
在第三章中,以65奈米金氧半場效電晶體製程實現一個具三維結構之K頻段高輸出功率變壓器結合式功率放大器。為了達到高輸出功率,以放射狀功率分配器及放射狀功率結合器實現八路的功率結合,此放射狀網路也同時具有阻抗轉換的功能以減少輸入及輸出端匹配網路因高阻抗轉換比所造成的損耗。由於放射狀架構使得功率分配器及功率結合器能夠以三維的結構在電路中央共用同一區域的面積,因此功率分配器及功率結合器所需佔用的面積將可大幅縮小。此功率放大器在K頻段達到最大的飽和輸出功率26.1dBm並同時保有良好的面積使用效率。
在第四章中,以180奈米金氧半場效電晶體製程實現一個2-GHz的Doherty功率放大器。將含有λ/4架構的被動元件在晶片外以FR-4板材實現,使晶片面積縮小並降低元件造成的損耗以提升效率。此功率放大器呈現20% 的功率附加效率 (PAE) 並在6 dB功率回退時 (power back-off) 仍保有19%的功率附加效率。


With the development of wireless communication, the radial frequency integrated circuit with CMOS technology is valued gradually in the industry. Among the transceiver, power amplifier is the most critical component. As the reasons, the design and analysis of CMOS power amplifier is focused in this thesis.
In chapter 2, an ultra-compact 24-GHz power amplifier implemented in 180-nm CMOS process. For compact chip size design, transformers are adopted to accomplish the functions of power combining, impedance matching and single-to-differential ended simultaneously. A virtual ground is generated at the symmetry of circuit by push-pull topology. DC bias can be fed directly without large value bypass capacitors, and the chip size is further reduced. The power amplifier achieves the smallest chip size 0.26 mm2 and the highest area efficiency around 24-GHz.
In chapter 3, a K-band high output power transformer combined power amplifier with 3-D architecture implemented in 65-nm CMOS process. In order to achieve high output power, 8-ways power combining is realized by the radial splitter and radial combiner. The radial networks with the function of impedance transformation to alleviate the loss of input and output matching networks caused by large impedance transformation ratio. Thanks to the radial structure, the power splitter and power combiner can share the center area of the circuit by a 3-D architecture, therefore the area occupied by power splitter and power combiner can be reduced significantly. The power amplifier achieves the highest saturated output power 26.1 dBm with excellent area efficiency at K-band.
In chapter 4, a 2-GHz Doherty power amplifier implemented in 180-nm CMOS process. All passive elements with λ/4 topology are fabricated off-chip on FR-4 board to diminish the chip size and mitigate the loss caused by elements to improve efficiency. The power amplifier performs 20% PAE and maintains 19% PAE at 6 dB power back-off.


誌謝 i
中文摘要 iii
ABSTRACT iv
CONTENTS vi
LIST OF FIGURES ix
LIST OF TABLES xv
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Contributions 2
1.3 Thesis Organization 2
Chapter 2 Ultra-Compact 24-GHz Power Amplifier 3
2.1 Power Combining Techniques 3
2.1.1 Direct Combining 3
2.1.2 Wilkinson Combining 5
2.1.3 Transformer 7
2.2 Design of Ultra-Compact 24-GHz Power Amplifier 9
2.2.1 Common Source and Cascode Topology 10
2.2.2 Bias Selection 11
2.2.3 Device Selection 12
2.2.4 Output Transformer 16
2.2.5 Input Balun 27
2.2.6 Design flow 31
2.2.7 Ultra-Compact Transformer-based Power Amplifier 32
2.3 Simulation Results 34
2.3.1 Small Signal Simulation 34
2.3.2 Large-signal Simulation 35
2.4 Experimental Results 37
Chapter 3 A Fully-Integrated K-band High Power Transformer Combined Power Amplifier With 3-D Architecture 41
3.1 Transformer Based Power Combining 42
3.1.1 Challenges for Fully-Integrated High Power PA in CMOS Process 42
3.1.2 TF-based Voltage-Combining Technique 44
3.1.3 TF-based Current-Combining Technique 50
3.2 Dual-Radial Symmetric Architecture [2], [22] 53
3.2.1 Radial Structure 53
3.2.2 Folded Transformer 55
3.2.3 3-D Architecture 57
3.3 Design of K-band High Power Transformer Combined Power Amplifier With 3-D Architecture 58
3.3.1 Design flow 58
3.3.2 Bias and Device Selection 59
3.3.3 Power Cell Using Folded Transformer 63
3.3.4 Radial Combiner and Splitter 71
3.3.5 I/O Matching Network 79
3.3.6 DC Consideration 81
3.3.7 Folded-TF-Based Power Amplifier with 3-D Architecture 83
3.4 Simulation Results 85
3.4.1 Small Signal Simulation 85
3.4.2 Large-signal Simulation 86
3.5 Experimental Results 88
Chapter 4 2-GHz CMOS Doherty Power Amplifier 94
4.1 Operation Principles of Doherty Amplifier 95
4.2 Design of 2-GHz CMOS Doherty Power Amplifier 100
4.2.1 Carrier Amplifier 100
4.2.2 Peaking Amplifier 104
4.2.3 Quarter-Wave Impedance Transformer 106
4.2.4 Input Power Splitter 108
4.2.5 Doherty Power Amplifier 112
4.3 Simulation Results 113
4.4 Experimental Results 117
Chapter 5 Conclusions 121
REFERENCE 122


[1]P.-C. Huang, J.-L. Kuo, Z.-M. Tsai, K.-Y. Lin, H. Wang, “A 22-dBm 24-GHz power amplifier using 0.18-μm CMOS technology,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp. 248-251.
[2]J.-F. Yeh, J.-H. Tsai, and T.-W. Huang, “A 60-GHz Power Amplifier Design Using Dual-Radial Symmetric Architecture in 90-nm Low-Power CMOS,” IEEE Trans. Microwave Theory Tech., vol. 61, no. 3, Mar. 2013.
[3]H. Wang, J.-H. Tsai, K.-Y. Lin, Z.-M. Tsai, and T.-W. Huang, “CMOS power amplifiers for millimeter-wave applications,” to appear in IEEE Microw. Mag.
[4]C. C. Hung, J. L. Kuo, K. Y. Lin, and H. Wang, “A 22.5-dB gain, 20.1-dBm output power K-band power amplifier in 0.18-μm CMOS,” IEEE RFIC Symp., pp. 557–560, May 2010.
[5]Guillermo Gonzales, Microwave Transistor Amplifier Analysis and Design, 2nd Edition, Prentice-Hall Inc., Englewood Cliffs, 1997.
[6]David M. Pozar, Microwave Engineering, 3rd Edition, John Wiley & Sons, Inc., Hoboken, New Jersey, 2005.
[7]廖信強撰,適用於高速傳輸系統之毫米波高鏡像抑制調變器設計與D頻帶功率放大器之研製,國立台灣大學電信工程研究所碩士論文,2012年7月。
[8]C. Y. Law and A.-V. Pham, “A high-gain 60 GHz power amplifier with 20 dBm output power in 90 nm CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2010, pp. 426–427.
[9]D. Chowdhury, P. Reynaert, and A. M. Niknejad, “A 60 GHz 1 V 12.3 dBm transformer-coupled wideband PA in 90 nm CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2008, pp. 560–635.
[10]W. L. Chan, J. R. Long, M. Spirito, and J. J. Pekarik, “A 60GHz-band 1 V 11.5 dBm power amplifier with 11% PAE in 65 nm CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2009, pp. 380–381.
[11]A.M. Niknejad, D. Chowdhury, and J. Chen, “Design of CMOS power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 6, pp. 1784–1796, Jun. 2012.
[12]I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, “Fully integrated CMOS power amplifier design using the distributed active-transformer architecture,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 371–383, Mar. 2002.
[13]I. Aoki, S. D. Kee, D. Rutledge, and A. Hajimiri, “Distributed active transformer: A new power combining and impedance transformation technique,” IEEE Trans. Microwave Theory Tech., vol. 50, no. 1, Jan. 2002.
[14]C.-S. Lin, P.-S. Wu, M.-C. Yeh, J.-S. Fu, H.-Y. Chang, K.-Y. Lin, and H. Wang,”Analysis of multiconductor coupled-line Marchand Baluns for miniature MMIC design,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 6, pp. 1190-1199, Jun. 2007.
[15]Yung-Nien Jen, Jheng-Han Tsai, Chung-Te Peng, and Tian-Wei Huang, “A 20 to 24 GHz 16.8 dBm fully integrated power amplifier using 0.18-μm CMOS process,” IEEE Microwave and Wireless Components Lett, vol. 19, no. 1, pp. 42- 44, Jan. 2009.
[16]Jing-Lin Kuo, Zuo-Min Tsa, Huei Wang, "A 19.1-dBm fully-integrated 24 GHz power amplifier using 0.18-l1m CMOS technology," in Proceeding of the European Microwave Conference. Oct. 2008. pp. 558-56l.
[17]A. Komijani and A. Hajimiri, “A 24 GHz, +14.5 dBm fully-integrated power amplifier in 0.18-μm CMOS,” in Proc. IEEE Custom Integr.Circuits Conf., Oct. 2004, pp. 561–564.
[18]Ghazinour, P. Wennekers, J. Schmidt, Y. Vi, R. Reuter, and J. Teplik, "A fully-monolithic SiGe-BiCMOS transceiver chip for 24 GHz applications," IEEE BCTM, pp. 181-184, 2003.
[19]J. Kim, W. Kim, H. Jeon, Y.-Y. Huang, Y. Yoon, H. Kim, C.-H. Lee, and K. T. Kornegay, “A fully-integrated high-power linear CMOS power amplifier with a parallel-series combining transformer,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 599–614, Mar. 2012.
[20]D. Lu, M. Kovacevic, J. Hacker, and D. Rutledge, "A 24 GHz active phased-array with a power amplifier/low-noise amplifier in MMIC," Int. J. Infrared Millimeter Waves vol. 23, pp. 693-704, May. 2002
[21]I. Gresham, A. Jenkins, R. Egri, C. Eswarappa, F. Kolak, R. Wohlert, 1. Bennett, and 1. P. Lanteri, "Ultra wide band 24GHz automotive radar front-end," in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2003, pp. 369-372
[22]J.-F. Yeh, J.-H. Tsai, and T.-W. Huang, “A multi-mode 60-GHz power amplifier with a novel power combination technique,” in RFIC Dig., Jun. 2012, pp. 61–64
[23]K.-C. Tsai and P. Gray, “A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications,” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 962–970, Jul. 1999.
[24]B. Francois and P. Reynaert, “A fully integrated watt-level linear 900-MHz CMOS RF power amplifier for LTE-applications,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 6, pp. 1878–1885, Jun. 2012.
[25]P. Haldi, D. Chowdhury, P. Reynaert, G. Liu, and A. M. Niknejad, “A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1054–1063, May 2008.
[26]P. Haldi, G. Liu, and A. M. Niknejad, “CMOS compatible transformer power combiner,” Electron. Lett., vol. 42, no. 19, pp. 1091–1092, Sep. 2006.
[27]Q. J. Gu, Z. Xu, and M.-C. F. Chang, “Two-way current-combining W-band power amplifier in 65-nm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 5, pp. 1365–1374, May 2012.
[28]B. Martineau, V. Knopik, A. Siligaris, F. Gianesello, and D. Belot, “A 53-to-68 GHz 18 dBm power amplifier with an 8-way combiner in standard 65 nm CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2010, pp. 428–429.
[29]K.-Y.Wang, T.-Y. Chang, and C.-K. Wang, “A 1 V 19.3 dBm 79 GHz power amplifier in 65 nm CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2012, pp. 260–262.
[30]Y. Kawano, A. Mineyama, T. Suzuki, M. Sato, T. Hirose, K. Joshin, “A Fully-Integrated K-band CMOS Power Amplifier with Psat of 23.8 dBm and PAE of 25.1 %,” in RFIC Dig., Jun. 2011, pp. 1-4.
[31]K. Joshin, Y. Kawano, M. Fujita, T. Suzuki, M, Sato, T. Hirose, “A 24 GHz 90-nm CMOS-based power amplifier module with output power of 20 dBm,” in IEEE International Symposium on Radio-Frequency Integration Technology, Singapore, Dec. 2009.
[32]M.M. Tarar, D. Kalim, R. Negra, “Asymmetric Doherty Power Amplifier at 2.2 GHz with 8.2 dB Output Power Back-Off,” in Microwave Conference (GeMiC), March 2012, pp. 1-4.
[33]T. Kitahara, T. Yamamoto, S. Hiura, “Doherty Power Amplifier with Asymmetrical Drain Voltages for Enhanced Efficiency at 8 dB Backed-off Output Power,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2011, pp. 1-4.
[34]C. Tongchoi, M. Chongcheawchamnan, and A. Worapishet, “Lumped element based Doherty power amplifier topology in CMOS process,” in Proc. IEEE Int. Symp. Circuits Syst., May 2003, vol. 1, pp. 445–448.
[35]蔡政翰撰,毫米波發射器線性化及十億位元無線通信系統,國立台灣大學電信工程研究所博士論文,2007年1月。
[36]E. Kaymaks琀 and P. Reynaert, “A 2.4 GHz fully integrated Doherty power amplifier using series combining transformer,” in Proc. ESSCIRC, 2010, pp. 302-305.
[37]L.-Y. Yang, H.-S. Chen, and Y.-J. Chen, “A 2.4 GHz fully integrated cascode-cascade CMOS Doherty power amplifier,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 3, pp. 197–199, Mar. 2008.
[38]C.-Y. Liu, T.-N. Luo, Yi-Jan Emery Chen and Deukhyoun Heo, “A 2.4 GHz CMOS Doherty power amplifier," IEEE International Microwave Symposium Digest, 2006, pp. 885-888.
[39]V. Saari, P. Juurakko, J. Ryynanen, and K. Halonen, "Integrated 2.4 GHz class-E CMOS power amplifier," in IEEE Radio Frequency integrated Circuits Symposium Dig., pp. 645 - 648, June 2005.


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊
 
系統版面圖檔 系統版面圖檔