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研究生:林秉賢
研究生(外文):Ping-Hsien Line
論文名稱:多核心堆疊記憶體架構中核心與記憶體電壓及頻率共同調控於熱效率表現之研究
論文名稱(外文):Exploring Synergistic DVFS Control of Cores and DRAMs for Thermal Efficiency in CMPs with 3D-stacked DRAMs
指導教授:楊佳玲楊佳玲引用關係
指導教授(外文):Chia-Lin Yang
口試委員:吳晉賢陳依蓉
口試委員(外文):Chin-Hsien WuYi-Jung Chen
口試日期:2013-07-29
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:資訊網路與多媒體研究所
學門:電算機學門
學類:網路學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:37
中文關鍵詞:功耗效率溫度控管三維多核系統微處理器設計
外文關鍵詞:Energy EfficiencyThermal Management3D Multicore SystemMicroarchitecture Design
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三維多核心堆疊記憶體架構已經被證實是一個有效的方法來解決傳統二維架構記憶體牆(Memory Wall)的問題,記憶體牆是記憶體速度不及處理器而造成系統效能瓶頸。由於三維多核心堆疊架構是將DRAM晶片堆疊在處理器的正上方增加了晶片耗能密度使得系統溫度升高,因此在此架構上如何控管溫度的方法是很重要的課題。在此架構上,記憶體與處理器以垂直堆疊方式整合,處理器因耗電發熱較多,會離散熱片最近。因此,離散熱片最遠的記憶體會散熱不易,通常為系統最熱的點(Hotspot)。此外,處理器產生的熱,會因熱堆疊效應積存於記憶體層。因此,傳統利用降低系統熱點的功率耗能之降溫方式,已不能有效夠控制系統溫度。在多核心堆疊記憶體架構上現有的調控溫度的方法為處理器電壓及頻率調控(Voltage-Frequency Scaling),此方法不只減少處理器耗能,也間接降低存取記憶體的速度進而減少了記憶體的耗能。然而,為了支援記憶體高頻寬的需求而使用大量的直通矽晶穿孔(TSVs),導致記憶體耗能功率增高,而使處理器不再是主要耗電來源。我們發現單純只控制處理器速度的方法並不能有效的讓系統散熱,尤其是需要大量記憶體存取的應用程式上。因此在本論文,我們提出了調控記憶體頻率來降低單次存取記憶體需要的耗能。我們的結果顯示共同調控核心與記憶體電壓及頻率的方法比起傳統只調控處理器的方法,能夠得到更高的散熱效能。

Chip-Multiprocessors (CMPs) with 3D-stacked DRAMs have been
demonstrated as a promising way to tackle the memory wall problem. Due to the increasing power density, 3D-stacked systems frequently operate at or near the thermal limit. Therefore, thermal management is critical to 3D ICs. For CMPs with 3D-stacked DRAMs, system hotspot is in DRAMs since DRAMs are in the layers farther from the heat sink than cores, and heat from the vertically aligned cores is also accumulated in DRAMs. Therefore, applying conventional thermal control methods that reduce power from the hotspot is not effective for CMPs with 3D-stacked DRAMs. Existing thermal management approaches for CMPs with 3D-stacked DRAM architecture perform DVFS (Dynamic Voltage/Freqnecy Scaling) on cores, which does not only reduce core power consumption but also DRAMs as well since it lowers DRAM access frequency. However, we find that core-side DVFS cannot effectively control temperature for memory-intensive workloads. That is because instantaneous memory burst due to high TSV density can easily overheat the system since DRAM layers have low efficiency in heat dissipation. Therefore, in this paper, we propose to apply DVFS on DRAMs to reduce DRAM access power. Our results show that synergistically controlling the voltage-frequency levels of cores and DRAMs
achieves higher thermal efficiency than controlling cores only.

Abstract i
1 Introduction 1
2 Background 6
2.1 The 3D Integration Technology . . . . . . . . . . . . . . . . . 6
2.2 CMP with 3D-stacked DRAMs . . . . . . . . . . . . . . . . . 8
3 Related Works 9
3.1 Analysis of the thermal behavior in 3D ICs . . . . . . . . . . . 9
3.2 Thermal managements for 3D ICs . . . . . . . . . . . . . . . . 10
3.3 Thermal managements for 2D ICs . . . . . . . . . . . . . . . . 11
4 Taxonomy of thermal control mechanisms for CMPs with
3D-stacked DRAMs 12
4.1 DRAM Bandwidth Throttling . . . . . . . . . . . . . . . . . . 12
4.2 Core DVFS/Shutdown . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Synergistic Core and DRAM DVFS . . . . . . . . . . . . . . . 14
5 Experimental Setup 16
5.1 Experimental platform . . . . . . . . . . . . . . . . . . . . . . 16
5.2 System con figurations . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Workloads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Evaluations of existing thermal control techniques 22
7 Analysis of synergistic DVFS control on cores and DRAMs 27
8 Conclusion 33
Bibliography 34

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