臺灣博碩士論文加值系統

本論文實現一個資訊安全系統的架構並評估它的機密資料傳輸的性能。進階加密標準(Advanced Encryption Standard ,AES)的Rijndael 演算法分為兩個部分加密和解密，其中皆使用疊代動作與128、192以及256位元的對稱密鑰區塊。AES系統架構由ShiftRow, SubByte, AddRoundKey以及MixColumn等四個模組所組成。提出以ROM為基底的CAM，可稱為內容可定址唯讀記憶體(Content Addressable Memory,CAROM)，用來實現SubByte與inv SubByte這兩個查表法的轉換查表模組在加密與解密過程中，並且改善處理時間與複雜度。CAROM電路使用TSMC 0.18um製程下線並驗證成功。另外，快取電路可被採用去取代原本的S-Box與inv S-Box，並被成功地設計及模擬出來。藉由Xilinx FPGA 開發平台，使用Verilog實現，使用CAROM模組與Cache模組於AES由Verilog規劃實現，系統的功能已成功驗證並分析其性能。其結果顯示CAROM電路比ROM在查表法的部份減少了許多邏輯元件，並達到87.8MHz較快的工作頻率，此結果顯示具CAROM之AES系統擁有較高速之資料加解密功能。

In the thesis, the structure of information security system was implemented and to evaluate its performance for the securely data transmit in the network. The Advanced Encryption Standard (AES) with Rijndael algorithm is divided into two major block encryption and decryption which is operated for the iteration and the symmetric password key block cryptography with 128, 196, and 256-bit. The AES structure has shiftRow, SubByte, AddRoundKey, and MixColumn 4 modules are combined. The ROM-base Content Addressable Memory (CAROM) used to realize 2 Look-Up-Table of the Sub-Byte and Inv-Sub-Byte transformation function in the encryption and decryption operation is proposed to improve the execution time and complexity. The CAROM circuit was designed and fabricated by HSPICE in TSMC 0.18m 1P6M technology. The Cache structure can be adopted to substitute for S-box and inverse S-box that the circuit is successfully designed and simulated. As the simulation results show that the functions and performance of the proposed AES system with the CAROM circuit and the Cache circuit are successfully verified by the Verilog in the Xilinx FPGA development platform. The used logic element of CAROM is effectively reduced than Look-Up-Table from read-only-memory. The higher frequency can be operated about 87.8MHz. The execution time of the AES system with CAROM has a more high-speed operated for the data Enc/Dec function.

摘要 II
Abstract III
目錄 1
圖目錄 3
表目錄 4
第一章 緒論 5
1.1 研究動機與目的 5
1.2 研究方向 5
1.3 論文架構 6
第二章 AES架構與演算法 7
2.1 AES演算法概述 7
2.1.1 AES數學模式 7
2.1.2 AES的輸入、輸出與陣列 11
2.2 AES加密演算法函數 12
2.2.1 SubBytes 15
2.2.2 ShiftRows 18
2.2.3 MixColumns函數 18
2.2.4 AddRoundKey 19
2.3 AES解密演算法函數 20
2.3.1 InvSubBytes 22
2.3.2 InvShiftRows 24
2.3.3 InvMixColumns 24
2.4 AES金鑰擴張(KeyExpansion) 25
第三章 應用於AES查表法之電路架構 27
3.1 唯讀記憶體 27
3.2 CAM 29
3.2.1 CAM架構 30
3.2.2 CAM基本定理 32
3.2.3 CAM細胞元電路 33
3.2.4 內容可定址唯讀記憶體 37
3.3 Cache 39
第四章 電路模擬與分析 46
4.1 HSPICE模擬結果 46
4.2 Verilog模擬與合成結果 53
4.2.1 AES系統加解密模擬結果 53
4.3 AES系統模組合成結果 56
4.3.1 AES系統使用ROM模組合成結果 57
4.3.2 AES系統使用CAROM模組合成結果 59
4.3.3 AES系統使用Cache模組合成結果 61
4.4 AES系統合成結果比較 62
第五章 結論 64
參考文獻 65
附錄 69

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