(3.210.184.142) 您好!臺灣時間:2021/05/12 04:06
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:陳冠勳
研究生(外文):Guan-Syun Chen
論文名稱:具氧化鋱電荷捕捉層之金氧半結構非揮發性記憶體元件特性研究
論文名稱(外文):Memory Characteristics of Metal-Oxide-Semiconductor Structured Nonvolatile Memory Capacitors with Terbium Oxides as Charge Trapping Layers
指導教授:鄭錦隆
學位類別:碩士
校院名稱:國立虎尾科技大學
系所名稱:光電與材料科技研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:111
中文關鍵詞:氧化鋱金氧半非揮發性記憶體元件高介電係數材料白金
外文關鍵詞:Terbium oxidesCMOSnonvolatile deviceshigh-k dielectricplatnium
相關次數:
  • 被引用被引用:0
  • 點閱點閱:173
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本論文以稀土元素氧化鋱(Tb4O7)作為金氧半結構非揮發性記憶體元件之電荷捕捉層。首先運用不同氣體及流量製作二氧化矽穿隧層及對氧化鋱電荷捕捉層施行沉積後氧化熱處理,藉由氮氣及氧氣調控金氧半結構非揮發性記憶體元件之記憶特性研究,接著改變不同電荷阻擋層厚度,最後探討白金(Pt)摻雜氧化鋱電荷捕捉層之記憶特性研究。透過量測元件的各個特性包含遲滯、寫入、抹除、耐久力及持久力等參數獲得最佳特性。
實驗結果顯示,氧化鋱電荷捕捉層的記憶特性主要是以電洞捕捉為主,與利用氧氣熱處理氧化鋱電荷捕捉層比較,則利用氮氣處理的氧化鋱具有比較大的記憶窗,同時具有較佳的寫入、抹除及耐久力等特性,而且氮氣量越大其記憶窗越大。相同寫入電壓下,阻擋層厚度20nm有最佳的電子捕獲特性,只要10-6秒就能將電荷寫入,反之10nm和25nm則需要10秒及1秒的時間。阻擋層厚度20nm的耐久力特性在經過1000次的寫入/抹除後,仍保持著優良的電特性,而10nm和25nm則撐不到10次反覆的寫入/抹除。摻雜白金在電荷捕捉層,在濺鍍時間50秒發現各種電特性都獲得極大的改善。記憶窗口比沒鍍白金時大了6.6伏,且因電子捕獲特性提升,電荷寫入特性及抹除特性所需時間及電壓都分別的降低,正電壓寫入的持久力特性經過4000秒後仍然保存著電荷,且寫入所需時間是其他製程參數元件的1/10,尤其耐久力特性變得極佳,經過1000次寫入/抹除後幾乎沒有電荷損失。


Memory characteristics of metal-oxide-semiconductor (MOS) structured nonvolatile memory capacitors with terbium oxides (Tb4O7) as charge trapping layers were demonstrated in this work. First, the memory characteristic of MOS structured nonvolatile memory capacitors with various tunneling oxide were demonstrated. Then, the SiO2/Tb4O7/SiO2 stacked films in MOS structured nonvolatile memory capacitors with various gas ambient treated Tb4O7 as charge trapping layers were proposed. Various gas ambient treatments include oxygen and nitrogen. Furthermore, the MOS structured nonvolatile memory capacitors with Tb4O7 charge trapping layers and various blocking oxide thicknesses were also investigated. Finally, the effects of various Pt-doped Tb4O7 as charge trapping layers of MOS structured nonvolatile memory capacitors were presented.
The results suggest that the memory effect is mainly due to the holes trapping. Compared with oxygen treatment, larger memory window can be achieved by incorporated more nitrogen into Tb4O7 dielectric. Furthermore, the better properties, including programming time, erasing time, and endurance, were presented by more nitrogen treated Tb4O7 dielectric as charge trapping layers. The programming time of 10-6 s for the sample with 20 nm of blocking oxide can be achieved. On the contrary, it should be 10 and 1 s for the other samples. The endurance of 1000 times for sample with the 20 nm of blocking oxide sample is better than that of the other samples. By tuning Pt-doped Tb4O7, the excellent memory characteristics, including the hysteresis, and the programming/erasing time, were be demonstrated. Compared with the sample without Pt-doped Tb4O7 dielectronics, there is a larger shift of 6.6 V for the sample with the sputtering time of 50 s. Moreover, the retension of 4000 s and the redurance of 1000 s were also be demonstrated for the sample with the sputtering time of 50 s.


摘要.....i
Abstract.....ii
誌謝.....iii
目錄.....iv
表目錄.....vi
圖目錄.....vii
第一章 緒論.....1
1.1高介電係數材料(High-k dielectric)研究發展文獻回顧.....1
1.2沉積後退火氣體處理及阻擋層厚度的影響文獻回顧.....2
1.3奈米晶體(Nanocrystals)研究發展文獻回顧.....3
1.4研究動機.....4
1.5論文架構.....4
第二章 元件製程與量測.....5
2.1使用不同氣體環境對SiO2穿遂氧化層做快速加熱退火處理.....5
2.1.1晶圓清洗處理.....5
2.1.2穿遂氧化層的製程.....5
2.1.3電荷捕獲層的製程.....5
2.1.4阻擋氧化層的製程.....6
2.1.5上下電極的製程.....6
2.2使用不同氣體環境對Tb4O7電荷捕獲層做沉積後氧化熱處理.....6
2.2.1晶圓清洗處理.....6
2.2.2穿遂氧化層的製程.....7
2.2.3電荷捕獲層的製程.....7
2.2.4阻擋氧化層的製程.....7
2.2.5上下電極的製程.....7
2.3沉積不同厚度的SiO2作為阻擋氧化層.....7
2.3.1晶圓清洗處理.....7
2.3.2穿遂氧化層的製程.....8
2.3.3電荷捕獲層的製程.....8
2.3.4阻擋氧化層的製程.....8
2.3.5上下電極的製程.....8
2.4對Tb4O7摻雜不同厚度的Pt作為電荷捕獲層.....8
2.4.1晶圓清洗處理.....9
2.4.2穿遂氧化層的製程.....9
2.4.3電荷捕獲層的製程.....9
2.4.4阻擋氧化層的製程.....9
2.4.5上下電極的製程.....9
2.5元件電特性與可靠度特性量測.....10
第三章 探討具氧化鋱電荷捕捉層之金氧半結構非揮發性記憶體元件
特性研究.....20
3.1 使用不同氣體環境對SiO2穿遂氧化層做快速加熱退火處理.....20
3.1.1結果與討論.....20
3.1.2結論.....22
3.2 使用不同氣體環境對Tb4O7電荷捕獲層做沉積後氧化熱處理.....22
3.2.1結果與討論.....22
3.2.2結論.....24
3.3 沉積不同厚度的SiO2作為阻擋氧化層.....25
3.3.1結果與討論.....25
3.3.2結論.....27
3.4 沉積不同厚度的Pt作為電荷捕獲層.....28
3.4.1結果與討論.....28
3.4.2結論.....30
第四章 結論與建議.....101
4.1結論.....101
4.2建議.....101
參考文獻.....102
英文論文大綱.....105
作者簡歷.....111

[1] Y. Yang, B. S. Lee, M. Lee, C. S. Jun, and T. S. Kim, “The Development of the Non-contact Electrical Leakage Property Measurement System for the High-K Dielectric Materials on DRAM Capacitors,’’ IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 7-11, May. 2006.
[2] W. Banerjee and S. Maikap, “High-k Hf-based Nanocrystal Memory Capacitors With IrO x Metal Gate for NAND Application,’’ IEEE International Workshop on Memory Technology, Design, and Testing, pp. 31-33, 2009.
[3] Y. Pei, C. Yin, M. Nishijima, T. Kojima, and T. Fukushima, “Formation of high density tungsten nanodots embedded in silicon nitride for nonvolatile memory application,’’ Appl. Phys. Lett., Vol. 94, No.06, pp.063108-1-063108-3, Feb. 2009.
[4] T. M. Pan, F. H. Chen, and J. S. Jung, “A high-k Tb2TiO5 nanocrystal memory,’’ Appl. Phys. Lett., Vol. 96, No.10, pp. 102904-1-102904-3, Mar. 2010.
[5] X. D. Huang, Johnny K. O. Sin, and P. T. Lai, “Nitrided La2O3 as Charge-Trapping Layer for Nonvolatile Memory Applications,’’ IEEE Trans. Device and Materials Reliability, Vol. 12, No. 2, pp. 306-310, Jun. 2012.
[6] Z. Jin, H. S. Kwok, and M. Wong, “High-Performance Polycrystalline SiGe Thin-Film Transistors Using Al2O3 Gate Insulators,’’ IEEE Electron Device Lett., Vol. 19, No. 12, pp. 502-504, Dec. 1988.
[7] P. C. Juan, C. Y. Chang, and Y. M. Lee, “A New Metal–Ferroelectric (PbZr0.53Ti0.47O3)–Insulator (Dy2O3)–Semiconductor (MFIS) FET for Nonvolatile Memory Applications,’’ IEEE Electron Device Lett., Vol. 27, No. 4, pp. 217-220, Apr. 2006.
[8] N. C. Su, S. J. Wang, and A. Chin, “Dielectric and structural characterization of high-temperature ferroelectric xBi(Zn1/2Ti1/2)O3−yPbZrO3–zPbTiO3 perovskite ternary solid solution,’’ Appl. Phys. Lett., Vol. 109, No. 07, pp. 094102-1-094102-1-7, Mar. 2011.
[9] N. C. Su, S. J. Wang, and A. Chin, “A Nonvolatile InGaZnO Charge-Trapping-Engineered Flash Memory With Good Retention Characteristics,’’ IEEE Electron Device Lett., Vol. 31 No. 3, pp. 201-203, Mar. 2010.
[10] J. M. J. Lopes, E. D. Ozben, M. Roeckerath, U. Littmark, R.Luptak, S. Lenk, A. Besmehn, U. Breuer, J. Schubert, and S. Mantl “Rare-earth based alternative gate dielectrics for future integration in MOSFETs,’’ IEEE Ultimate Integration of Silicon, pp. 99-102, Mar. 2009.
[11] P. C. Juan, C. Y. Chang, and Y. M. Lee, “A New Metal–Ferroelectric (PbZr0.53Ti0.47O3)–Insulator (Dy2O3)–Semiconductor (MFIS) FET for Nonvolatile Memory Applications,’’ IEEE Electron Device Lett., Vol. 27, No. 4, pp. 217-220, Apr. 2006.
[12] C. H. Chen, C. H. Liao, C. T. Lin, J. C. Wang, P. W. Huang, and C. S. Lai “Effects of HfO2 Trapping Layer in Gd2O3 Nanocrystal Nonvolatile Memory with Multi-tunneling Layers,’’ IEEE Electron Devices and Solid-State Circuits, pp. 1-3, Nov. 2011.
[13] S. Y. Huang, T. C. Chang, M. M. Chen, S. M. Sze, and M. J. Tsai, “Investigation of Resistive Switching Properties in Sm2O3 Memory Devices,’’ IEEE Non-Volatile Memory Technology Symposium, pp. 1-3, Nov. 2011.
[14] T. M. Pan, and J. W. Chen, “Metal-oxide-high-k-oxide-silicon memory structure using an Yb2O3 charge trapping layer,’’ Appl. Phys. Lett., Vol. 93, No. 18, pp. 183510-1-183510-3, Nov. 2008.
[15] F. H. Chen, T. M. Pan, and F. C. Chiu, “Metal–Oxide–High- k -Oxide–Silicon Memory Device Using a Ti-Doped Dy2O3 Charge-Trapping Layer and Al2O3 Blocking Layer,’’ IEEE Trans. Electron Devices Lett., Vol. 58, No. 11, pp. 3847-3851, Nov. 2011.
[16] C. H. Kao, H. Chen, K. S. Chen, P. L. Lai, S. N. Cheng, C. J. Liao, H. Y. Wang, C .H. Hsieh, and C. H. Lin “Electrical and Physical Characteristics of the High-K Tb2O3 (Terbium) Dielectric Deposited on the Polycrystalline Silicon,’’ IEEE Solid-State and Integrated Circuit Technology, pp. 1039-1041, Nov. 2010.
[17] T. M. Pan, J. S. Jung, and F. H. Chen “Metal-oxide-high-k-oxide-silicon memory structure incorporating a Tb2O3 charge trapping layer,’’ Appl. Phys. Lett., Vol. 97, No. 12, pp. 012906-1-012906-3, Jul. 2010.
[18] T. M. Pan, and Z. H. Li “High-performance CF4 plasma treated polycrystalline silicon thin-film transistors using a high-k Tb2O3 gate dielectric,’’ Appl. Phys. Lett., Vol. 96, No. 11, pp. 113504-1-113504-3, Mar. 2010.
[19] T. M. Pan, J. S. Jung, and F. H. Chen “Structural and electrical characteristics of high-k Tb2O3 and Tb2TiO5 charge trapping layers for nonvolatile memory applications,’’ Appl. Phys. Lett., Vol. 108, No. 07, pp. 074501-1-074501-5, Oct. 2010.
[20] T. M. Pan, F. H. Chen, and J. S. Jung, “Structural and Electrical Properties of Tb2 TiO5 Charge Trapping Layer Memories,’’ IEEE Electron Device Lett., 978-1-4244-5261-3, pp. 293-295, Feb. 2010.
[21] R. B. van Dover “Amorphous lanthanide-doped TiOx dielectric films,’’ Appl. Phys. Lett., Vol. 74, No. 30, pp. 3041-1-3041-3, Mar. 1999.
[22] C. X. Li, P. T. Lai, J. P. Xu, and X. Zou, “Effects of annealing gas on electrical properties and reliability of Ge MOS capacitors with HfTiON as gate dielectric,’’ IEEE Electron Devices and Solid-State Circuits, pp. 185-188, Nov. 2007.
[23] C. X. Li, P. T. Lai, J. P. Xu, and H. X. Xu, “Effects ofannealing gas species on the electrical properties and reliability of Ge MOS capacitors with high-k Y203 gate dielectric,’’ IEEE Electron Devices and Solid-State Circuits, pp. 243-246, Dec. 2009.
[24] S. S. Chung, P. Y. Chiang, G. Chou, C. T. Huang, P. Chen, C. H. Chu, and C. H. Hsu, “A Novel Leakage Current Separation Technique in a Direct Tunneling Regime Gate Oxide SONOS Memory Cell,’’ IEEE Electron Devices Meeting, pp. 26.1.1-26.1.4, Dec. 2003.
[25] Y. T. Lin, P. Y. Chiang, C. S. Lai, G. Chou, S. S. Chung, C. T. Huang, P. Chen, C. H. Chu, and C. H. Hsu, “New Insights into the Charge Loss Components in a SONOS Flash Memory Cell Before and After Long Term Cycling,’’ IEEE Physical and Failure Analysis of Integrated Circuits, pp.239-242, Jul. 2004.
[26] C. H. Chen, P. Y. Chiang, S. S. Chung, T. Chen, C. W. Chou, and C. H. Chu, “Understanding of the Leakage Components and Its Correlation to the Oxide Scaling on the SONOS Cell Endurance and Retention,’’ IEEE VLSI Technology, Systems, and Applications, pp. 1-2, Apr. 2006.
[27] D. H. Li, W. Kim, J. H. Lee, and B. G. Park, “Thickness-Dependence of Oxide-Nitride-Oxide Erase Property in SONOS Flash Memory,’’ IEEE Semiconductor Device Research Symposium, pp. 1-2, Dec. 2009.
[28] J. Y. Tseng, C. W. Cheng, S. Y. Wang, T. B. Wu, and K. Y. Hsieh “Memory characteristics of Pt nanocrystals self-assembled from reduction of an embedded PtOx ultrathin film in metal-oxide-semiconductor structures,’’ Appl. Phys. Lett., Vol. 85, No. 25, pp. 2595-1-2595-3, Jul. 2004.
[29] P.K. Singh,R. Hofmann, K. K. Singh, N. Krishna, and S. Mahapatra, “Nitrided La2O3 as Charge-Trapping Layer for Nonvolatile Memory Applications,’’ IEEE Trans. Electron Devices., Vol. 56, No. 9, pp. 2065-2072, Sep. 2009.
[30] P. K. Singh, G. Bisht, K. Auluck, M. Sivatheja, R. Hofmann, K. K. Singh, and S. Mahapatra, “Performance and Reliability Study of Single-Layer and Dual-Layer Platinum Nanocrystal Flash Memory Devices Under NAND Operation,’’ IEEE Trans. Electron Devices., Vol. 57, No. 8, pp. 1829-1837, Aug. 2010.
[31] J. Dufourcq, S. Bodnar, G. Gay, D. Lafond, and P. Mur “High density platinum nanocrystals for non-volatile memory applications,’’ Appl. Phys. Lett., Vol. 92, No. 07, pp. 073102-1-073102-3, Feb. 2008.
[32] Z. Xu, C. Zhu, Z. Huo, Y. Cui, and Y. Wang “Improved performance of non-volatile memory with Au-Al2O3 core-shell nanocrystals embedded in HfO2 matrix,’’ Appl. Phys. Lett., Vol. 100, No. 20, pp. 203509-1-203509-4, May. 2012.
[33] V. Mikhelashvili, B. Meyler, S. Yoffis, Y. Shneider, and A. Zeidler “Nonvolatile low-voltage memory transistor based on SiO2 tunneling and HfO2 blocking layers with charge storage in Au nanocrystals,’’ Appl. Phys. Lett., Vol. 98, No. 21, pp. 212902-1-212902-4, May. 2011.
[34] Y. Pei, C. Yin, M. Nishijima, T. Kojima, and T. Fukushima “Formation of high density tungsten nanodots embedded in silicon nitride for nonvolatile memory application,’’ Appl. Phys. Lett., Vol. 94, No. 06, pp. 063108-1-063108-3, Feb. 2009.
[35] V. Mikhelashvili, B. Meyler, S. Yoffis, Shneider, and J. Salzman “Ultraviolet to near infrared response of optically sensitive nonvolatile memories based on platinum nano-particles and high-k dielectrics on a silicon on insulator substrate,’’ Appl. Phys. Lett., Vol. 113, No. 07, pp. 074503-1-074503-6, Feb. 2013.
[36] V. Mikhelashvili, B. Meyler, S. Yoffis, J. Salzman, and M. Garbrecht “A nonvolatile memory capacitor based on Au nanocrystals with HfO2 tunneling and blocking layers,’’ Appl. Phys. Lett., Vol. 95, No. 02, pp. 023104-1-023104-3, Jul. 2009.
[37] Q. Wang, R. Jia, W. L. Li, W. H. Guan, Q. Liu, Y. Hu ,S. B. Long, B. Q. Chen, M. Liu, T. C. Ye, W. S. Lu, and L. Jiang, “A Hybrid Method For Fabrication Of Au Nanocrystals Nonvolatile Memory,’’ IEEE Nanotechnology, pp. 938-941, Aug. 2007.
[38] J. Lee, H. Kim, T. Park, Y. Ko, and J. Ryu “Charge trapping characteristics of Au nanocrystals embedded in remote plasma atomic layer-deposited Al2O3 film as the tunnel and blocking oxides for nonvolatile memory applications,’’ Vacuu. Scie. Tech. A., Vol. 30, No. 01, pp. 01A104-1-01A104-6, Sep. 2011.
[39] C. W. Hu, T. C. Chang, P. T. Liu, C. H. Tu, S. K. Lee, S. M. Sze, C. Y. Chang, B. S. Chiou, and T. Y. Tseng “Formation of cobalt-silicide nanocrystals in Ge-doped dielectric layer for the application on nonvolatile memory,’’ Appl. Phys. Lett., Vol. 92, No. 15, pp. 152115-1-152115-3, Apr. 2008.
[40] C. Sargentis, K. Giannakopoulos, A. Travlos, and D. Tsamakis, “A Comparative Study of Mos Memory Structures that Contain Platinum or Gold Nanoparticles,’’ IEEE Semiconductor Device Research Symposium, pp. 1-2, Aug. 2007.
[41] J. T. Jeng, and G. S. Chen, “Automatic measurement systems for electrical and reliability characteristics of nonvolatile memory devices“ International J. Intelligent Systems Science and Technology, vol. 3, No. 2, pp. 49-56, 2011.


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔