(3.238.235.155) 您好!臺灣時間:2021/05/16 06:47
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:廖家正
研究生(外文):Jia-Zheng Liao
論文名稱:CMOS參考電壓設計
論文名稱(外文):Design of A CMOS Reference Voltage
指導教授:劉偉行劉偉行引用關係
學位類別:碩士
校院名稱:國立虎尾科技大學
系所名稱:電子工程系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:76
中文關鍵詞:差動模式參考電壓溫度係數電流鏡運算放大器
外文關鍵詞:differential modereference voltagetemperature coefficientcurrent mirroroperational amplifier
相關次數:
  • 被引用被引用:6
  • 點閱點閱:462
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本論文提出一種CMOS差動模式輸出參考電壓電路。本電路藉由適當的組合具有正溫度係數與負溫度係數的參數以完成具有零溫度係數的參考電壓。並基於傳統之能隙參考電壓電路架構加以改善,加入由電流鏡組成之與絕對溫度成正比的電流源。相較於已知電路,本論文提出之電路不需要使用運算放大器,具有架構簡單、較少晶片面積,與較低功率消耗等優點。本論文除了詳細敘述工作原理以外,並使用HSPICE與LAKER電路模擬軟體以0.35微米和0.18微米製程參數進行佈局前與佈局後模擬以及晶片實作。模擬結果顯示本論文所提出之差動模式輸出參考電壓電路,當供應電壓為3.3V,溫度變化從-20˚C遞增至120˚C時,輸出電壓變化是1.3mV(0.225%),功率消耗為2.354 mW,溫度係數為16.11 ppm/˚C。此外,若將差動模式輸出參考電壓電路中移除一個電晶體與一個電阻後,電路即變成一個單端輸出模式且具有零溫度係數的參考電壓。當供應電壓為2.8V,溫度變化從-20˚C遞增至120˚C時,輸出電壓變化是2.01mV(0.387%),功率消耗為1.412 mW,溫度係數為27.79 ppm/˚C。模擬結果與理論推導相符合,也證明電路的可行性。本論文所提出之CMOS差動模式輸出參考電壓電路可適用於各種類比積體電路。

In this thesis, a CMOS differential-mode reference voltage circuit has been proposed. By properly using the positive and negative temperature coefficient parameters, a zero temperature-coefficient can be achieved. The proposed circuits are based on the traditional bandgap voltage reference circuit architecture with an additional current mirror and a proportional-to-absolute-temperature current source which is composed of current mirrors. As compared with the existed differential-mode reference voltage circuit, the proposed circuit does not need an operational amplifier, therefore it benefits from simpler circuit architecture, less chip area, and less power consumption. Besides the detailed design principle, the HSPICE and LAKER simulation program with 0.35-um and 0.18-um process parameters have been used to perform the pre-layout and post-layout simulation. According to the post-layout simulation results, as the supply voltages is 3.3V, the differential-mode output voltage reference circuit shows that, as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 1.3mV(0.225%), the corresponding power dissipation is 2.354mW and the temperature-coefficient is 16.11 ppm/˚C. In addition, if a transistor and a resistor are removed from the proposed differential-mode output voltage reference circuit, a single-ended mode reference voltage with zero temperature coefficient can be obtained. According to the post-layout simulation results, when the supply voltages is 2.8V, and as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 2.01mV(0.387%), the corresponding power dissipation is 1.412mW and the temperature-coefficient is 27.79 ppm/˚C.
All the simulation results are consistent with the theoretic analysis. The proposed circuits can be applied to different analog circuits.


摘要-----------------------------------------------i
Abstract-------------------------------------------ii
誌謝-----------------------------------------------iv
目錄-----------------------------------------------v
表目錄---------------------------------------------vii
圖目錄---------------------------------------------viii
符號說明-------------------------------------------xi
第一章 緒論---------------------------------------1
1.1 研究動機--------------------------------------1
1.2 積體電路的發展背景----------------------------1
1.3 設計流程--------------------------------------2
1.4 論文架構--------------------------------------4
第二章 傳統參考電壓工作原理-----------------------5
2.1 能隙參考電壓產生電路簡介----------------------5
2.2 能隙參考電壓基本原理--------------------------6
2.2.1 負溫度係數電壓------------------------------7
2.2.2 正溫度係數電壓------------------------------8
2.3 傳統之參考電壓電路----------------------------9
2.4 傳統參考電流源--------------------------------11
2.4.1 PTAT----------------------------------------11
2.4.2 PTAT2---------------------------------------12
2.5 傳統參考電壓源輸出級--------------------------14
2.6 能隙參考電壓電路------------------------------15
2.6.1 啟動電路------------------------------------18
2.6.2 串聯式能隙參考電壓電路----------------------20
2.6.3 實際佈局後模擬------------------------------22

第三章 改良式參考電壓電路-------------------------23
3.1 已知差動模式輸出參考電壓電路------------------23
3.2 改良式差動模式輸出參考電壓電路----------------25
3.2.1 電路工作原理--------------------------------25
3.3 單端模式輸出參考電壓電路----------------------28
3.4 使用疊接式電流鏡的參考電壓電路----------------29
3.4.1 電路的工作原理------------------------------30
第四章 模擬與量測結果-----------------------------33
4.1 設計流程--------------------------------------33
4.2 電路模擬結果----------------------------------35
4.2.1 能隙參考電壓電路----------------------------35
4.2.2 差動模式輸出參考電壓電路--------------------41
4.2.3 單端模式輸出參考電壓電路--------------------46
4.2.4 使用疊接式電流鏡之差動模式輸出參考電壓電路--50
4.2.5 使用疊接式電流鏡之單端模式輸出參考電壓電路--55
4.3 電路晶片實現與晶片量測結果--------------------60
4.3.1 能隙參考電壓電路----------------------------60
4.3.2 差動模式輸出參考電壓電路--------------------63
4.3.3 單端模式輸出參考電壓電路--------------------67
第五章 結論---------------------------------------70
參考文獻-------------------------------------------71
Extended Abstract----------------------------------73
簡歷(CV)-------------------------------------------76



[1]B. Razavi, 2001, “Design of Analogue CMOS Integrated Circuits,” McCraw-Hill Companies Inc, Boston, MA.
[2]吳昶明,2009,“低功率參考電壓源電路及LDO研究於實現”,國立聯合大學,電子工程研究所碩士論文。
[3]李民慶,蔡一名,許瑞軒,吳明峰,林建宏,張昇瑋,2008,“CMOS能隙參考電壓電路分析與設計”,亞東學報,28期,頁49~56,6月。
[4]李民慶,王清松,彭君晏,2006,“CMOS 帶差電壓參考電路之實作” ,亞東學報,26期,頁55~60,5月。
[5]Ge Tao, Fu Xiansong, Niu Pingjuan, Yang Guanghua, and Gao Tiecheng, 2010, “High-performance floating output bandgap circuit,” 2010 2nd International Conference on Signal Processing Systems, vol.3, pp. 224 – 226, Dalian, July.
[6]Marco Ferro, Franco Salerno, and Rinaldo Castello, 1988 “A Floating CMOS Bandgap Voltage Reference for Differential Applications,” Fourteenth European Solid-State Circuits Conference, pp.219 – 222, Manchester, UK, September.
[7]Todd L. Brook, and Alan L. Westwick, 1994, “A Low-Power Differential CMOS Bandgap Reference,” 1994 IEEE International Solid-State Circuits Conference, pp.248 – 249, San Francisco, CA, USA, February.
[8]陳郡豪,2006 ,“工作於次臨界區本體推動之低電壓低電流微型運算放大器”, 國立聯合大學,電子工程研究所碩士論文。
[9]賴立峰,2004,“以 NMOS電阻作0.2ppm/℃曲線補償能隙參考電壓電路”,國立交通大學,電機與控制工程學系碩士論文。
[10]Luiz L. G. Vermaas, Carlos R. T. de Mori, Robson L. Moreno, Adriano M. Pereira, 1998, “A Bandgap Voltage Reference Using Digital CMOS Process,” 1998 IEEE International Conference on Electronics, vol.2,pp. 303 – 306, Lisboa, September.
[11]K. E. Kujik, 1973, “A Precision Reference Voltage Source,” IEEE J. of Solid-State Circuits, vol.8, pp. 222 – 226, June.
[12]Dong-Ok Han, Jeong-Hoon Kim, and Nam-Heung Kim, 2008, “ Design of bandgap reference and current reference generator with low supply voltage,” 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, pp.1733 – 1736, Beijing, October.
[13]Na Sun and R. Sobot, 2010, “A low-power low-voltage bandgap reference in CMOS,” 2010 23rd Canadian Conference on Electrical and Computer Engineering, pp.1 – 5, Calgary, May.
[14]Edward K.F. Lee, 2010, “Low Voltage CMOS Bandgap References with Temperature Compensated Reference Current Output,” 2010 IEEE International Symposium on Circuits and Systems, pp.1643 – 1646, Paris, June.
[15]Henri J. Oguey, and Daniel Aebischer, 1996, “CMOS Current Reference Without Resistance,” The 22nd European Solid-State Circuits Conference, pp.140 – 107, Neuchatel, Switzerland, September.
[16]Gabriel A. Rincon-Mora, 2002, “Voltage References–From Diodes to Precision High-Order Bandgap Circuits,” The Institute of Electrical and Electrical Engineers, Inc.
[17]Bang-Sup Song, and Paul R. Gray, 1983, “A precision curvature-compensated CMOS bandgap reference,” IEEE Journal of Solid-State Circuits, pp.634 – 643, December.
[18]Edward K. F. Lee, 2009, “A low voltage CMOS bandgap reference without using an opamp,” IEEE International Symposium on Circuits and Systems, pp.2533 – 2536, Taipei, May.
[19]Paul R. Gray, Robert G. Meyer, 2001, “Analysis and Design of Analog Integrated Circuit,” 4th Edition, John Wiley & Sons, Inc.
[20]Chia-Wei Chang, Tien-Yu Lo, Chia-Min Chen, Kuo-Hsi Wu, and Chung-Chih Hung, 2007, “A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation,” IEEE International Symposium on Circuits and Systems, pp.3844 – 3847, New Orleans, LA, May.


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top