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論文名稱(外文):A novel dual-rail circuit structure for self-timed function blocks
外文關鍵詞:dual-rail, dynamic logic, asynchronous, self-time, low power, matched delay
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以最差路徑的映對延遲訊號取代而非互補其功能,且滿足給定的限制為設計的基礎目標。我們以TSMC 0.18um製程對本架構做模擬與驗證,證實比傳統雙軌式骨牌邏輯架構面積節省約37%的佈局面積,功率消耗降低約22.6%、速度提升了13.8%,顯示本電路樣板在實現越複雜的電路時,效能明顯提升,更突顯出本架構的特色。
As the time advance, there are various electronic products available on the market. Cannot effectively improve the capacity of the battery in handheld electronic products, reduce the overall power consumption of the circuit are what the electronic industry focuses on. In the process of searching the way to provide a better solution, advantage such as low power consumption, modularity, no clock skew and low EMI are discovered to fulfill the needs of the industrial intents. Thus, this thesis aims on the low power design, and by the aspect of achieving power saving, the same methodology is adopted to assist designers to implement highly efficient self-timed circuit modules.
A high efficient design template of self-timed modules, so call functional blocks, is introduced in this paper. The proposed template mimics traditional dual-rail logics to provide complementary outputs that can be used for generating a completion signal easily. The template gives designers totally freedom to develop high quality self-timed modules according to the most beneficial design factors, such as power, speed, area, or mix of them. This template behaves very much like a DCVSL circuit or dual-rail domino logics circuit; thus, we named it as pseudo DCVSL template.
Instead of implementing the both complementary functions, we replace one of them with a worst-case matched delay. And, which block to be chosen is based on the design goal to fulfill the given constraints. The template has carefully examined using TSMC 0.18um fabrication technology for the post-layout simulation and verification of the architecture. Comparing with the traditional dual-rail domino logics structures, 37% area saving, 22.6% lower power and 13.8% speedup. The feature of the pseudo DCVSL template works even better when the function block is more complex the circuit implementation. Thus, this circuit sample is showing an outperformed result.
摘  要 i
Abstract ii
誌  謝 iii
目  錄 iv
圖目錄 vi
表目錄 vii
第一章 緒論 1
1.1 研究動機與目的 1
1.2 同步與非同步電路簡介 2
1.3 論文內容概要 4
第二章 背景研究 5
2.1 自我時序資料路徑 5
2.1.1 自我時序元件 6
2.1.2 資料包裹通訊協定 7
2.1.3 資料包裹與延遲匹配 10
2.2 動態邏輯電路簡介 11
2.2.1 動態邏輯電路運作原理 12
2.2.2 骨牌式CMOS電路 14
2.2.3 骨牌式CMOS電路的設計考量 15
2.2.4 雙軌式骨牌邏輯電路 17
2.2.5 差動電壓開關邏輯電路 19
2.3 完成偵測的技巧 20
2.3.1 C元件 20
第三章 半包裹延遲DCVSL架構簡介 22
3.1 半包裹式DCVSL電路 22
3.1.1 非對稱延遲線 23
3.1.2 DVCSL完成偵測區塊 23
3.1.3 差動拴鎖器 24
3.1.4 檢知訊號產生器 25
3.2 延遲元件的選擇 26
3.2.1 串接式反相器延遲元件 26
3.2.2 傳輸閘延遲元件 27
3.2.3 數位可程式化延遲元件 28
3.3 新型雙軌式自我時序電路介紹 29
3.3.1 基本區塊 30
3.3.2 函數區塊 31
3.3.3 映對延遲區塊 33
第四章 電路驗證與實驗數據分析 34
4.1 晶片的測試與環境考量 34
4.1.1 輸入訊號的整型 34
4.1.2 輸出負載 37
4.2 延遲差異小的函數區塊驗證 38
4.2.1 佈局面積比較 38
4.2.2 功率消耗與延遲時間比較 40
4.3 延遲差異大的函數區塊驗證 41
4.3.1 佈局面積比較 41
4.3.2 功率消耗與延遲時間比 42
4.3.3 製程與溫度變異之模擬 43
第五章 結論與未來展望 45
參考文獻 46
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