(3.238.96.184) 您好!臺灣時間:2021/05/18 16:38
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

: 
twitterline
研究生:張哲齊
研究生(外文):Chang,Che-Chi
論文名稱:新型雙軌電路結構的自我時序功能區塊
論文名稱(外文):A novel dual-rail circuit structure for self-timed function blocks
指導教授:楊榮林楊榮林引用關係
指導教授(外文):Yang,Jung-Lin
學位類別:碩士
校院名稱:南台科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:102
畢業學年度:101
語文別:中文
論文頁數:48
中文關鍵詞:雙軌式、動態邏輯、非同步、自我時序電路、低功率、映對延遲
外文關鍵詞:dual-rail, dynamic logic, asynchronous, self-time, low power, matched delay
相關次數:
  • 被引用被引用:0
  • 點閱點閱:124
  • 評分評分:
  • 下載下載:6
  • 收藏至我的研究室書目清單書目收藏:0
隨著時代進步,市面上的電子產品日新月異,手持式電子產品在電池容量無法有效提升情況下,降低電路的整體功耗成為電子產業所重視的課題。在尋求解決的方法時,發現非同步電路具有低功率消耗、易模組化、無時脈偏移、低電磁波干擾等優點符合業界所需。因此本論文將針對這部分提出一個以低功率消耗為出發點的電路設計方式來協助設計者以動態電路開發高效能自我時序電路樣板。
本論文提出一個高效能自我時序設計樣板,類似傳統的雙軌邏輯電路並產生一個完成偵測訊號以提供互補輸出。電路的設計者能自由地取捨最有利的因素來開發電路例如功耗、速度、面積或多項。電路的運作方式類似傳統式DCVSL電路和雙軌骨牌式邏輯電路,因此我們將其命名為新型雙軌式自我時序電路樣板。
以最差路徑的映對延遲訊號取代而非互補其功能,且滿足給定的限制為設計的基礎目標。我們以TSMC 0.18um製程對本架構做模擬與驗證,證實比傳統雙軌式骨牌邏輯架構面積節省約37%的佈局面積,功率消耗降低約22.6%、速度提升了13.8%,顯示本電路樣板在實現越複雜的電路時,效能明顯提升,更突顯出本架構的特色。
As the time advance, there are various electronic products available on the market. Cannot effectively improve the capacity of the battery in handheld electronic products, reduce the overall power consumption of the circuit are what the electronic industry focuses on. In the process of searching the way to provide a better solution, advantage such as low power consumption, modularity, no clock skew and low EMI are discovered to fulfill the needs of the industrial intents. Thus, this thesis aims on the low power design, and by the aspect of achieving power saving, the same methodology is adopted to assist designers to implement highly efficient self-timed circuit modules.
A high efficient design template of self-timed modules, so call functional blocks, is introduced in this paper. The proposed template mimics traditional dual-rail logics to provide complementary outputs that can be used for generating a completion signal easily. The template gives designers totally freedom to develop high quality self-timed modules according to the most beneficial design factors, such as power, speed, area, or mix of them. This template behaves very much like a DCVSL circuit or dual-rail domino logics circuit; thus, we named it as pseudo DCVSL template.
Instead of implementing the both complementary functions, we replace one of them with a worst-case matched delay. And, which block to be chosen is based on the design goal to fulfill the given constraints. The template has carefully examined using TSMC 0.18um fabrication technology for the post-layout simulation and verification of the architecture. Comparing with the traditional dual-rail domino logics structures, 37% area saving, 22.6% lower power and 13.8% speedup. The feature of the pseudo DCVSL template works even better when the function block is more complex the circuit implementation. Thus, this circuit sample is showing an outperformed result.
摘  要 i
Abstract ii
誌  謝 iii
目  錄 iv
圖目錄 vi
表目錄 vii
第一章 緒論 1
1.1 研究動機與目的 1
1.2 同步與非同步電路簡介 2
1.3 論文內容概要 4
第二章 背景研究 5
2.1 自我時序資料路徑 5
2.1.1 自我時序元件 6
2.1.2 資料包裹通訊協定 7
2.1.3 資料包裹與延遲匹配 10
2.2 動態邏輯電路簡介 11
2.2.1 動態邏輯電路運作原理 12
2.2.2 骨牌式CMOS電路 14
2.2.3 骨牌式CMOS電路的設計考量 15
2.2.4 雙軌式骨牌邏輯電路 17
2.2.5 差動電壓開關邏輯電路 19
2.3 完成偵測的技巧 20
2.3.1 C元件 20
第三章 半包裹延遲DCVSL架構簡介 22
3.1 半包裹式DCVSL電路 22
3.1.1 非對稱延遲線 23
3.1.2 DVCSL完成偵測區塊 23
3.1.3 差動拴鎖器 24
3.1.4 檢知訊號產生器 25
3.2 延遲元件的選擇 26
3.2.1 串接式反相器延遲元件 26
3.2.2 傳輸閘延遲元件 27
3.2.3 數位可程式化延遲元件 28
3.3 新型雙軌式自我時序電路介紹 29
3.3.1 基本區塊 30
3.3.2 函數區塊 31
3.3.3 映對延遲區塊 33
第四章 電路驗證與實驗數據分析 34
4.1 晶片的測試與環境考量 34
4.1.1 輸入訊號的整型 34
4.1.2 輸出負載 37
4.2 延遲差異小的函數區塊驗證 38
4.2.1 佈局面積比較 38
4.2.2 功率消耗與延遲時間比較 40
4.3 延遲差異大的函數區塊驗證 41
4.3.1 佈局面積比較 41
4.3.2 功率消耗與延遲時間比 42
4.3.3 製程與溫度變異之模擬 43
第五章 結論與未來展望 45
參考文獻 46
[1]I. E. Sutherland, “Micropipelines,” in Communications of the ACM, vol. 32, pp. 720–738,June 1989.
[2]Devadas S. and A. R. Newton, “Exact Algorithms for Output Encoding, State Assignment and Four Level Boolean Minimization,” IEEE Trans. on CAD, 10(1), pp. 13-27, Jan. 1991.
[3]J. Sparsø, S. Furber, “Principles of Asynchronous Circuit Design,” Kluwer Academic Publishers, Boston, 2001.
[4]Jung-Lin Yang and Erik Brunvand, “Using Dynamic Domino Circuits in Self-Timed Systems, ” Great Lakes Symposium on VLSI, April 2003.
[5]M. Michael Vai , “VLSI DESIGN, ” CRC PRESS, Summer, 2000.
[6]Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, and Steve Kang, “High-Speed CMOS Circuits with Parallel Dynamic Logic and Speed-enhanced Skewed Static Logic,” IEEE Tran. on Circuits and Systems ∥, vol. 49, no. 6, pp. 434-439, Jun. 2002.
[7]Seok-Soo Yoon, Seok-Ryong Yoon, Seon-Wook Kim, Chulwoo Kim, "Charge-Sharing-Problem Reduced Split-Path Domino Logic,” VLSID, pp.201, 17th International Conference on VLSI Design, 2004.
[8]黃伯寬,邱威豪,林浩仁。減輕Domino電路電荷分享之雙重路徑架構設計。Journal of Science and Engineering Technology,第1 卷,第3 期,頁37 -45。
[9]I. Yonghee, K. Roy, “A logic-aware layout methodology to enhance the noise immunity of domino circuits,” Proceedings of the 2003 International Symposium on Circuits and Systems, Vol. 5, 2003, pp637-640.
[10]Weidong Kuang; Enjun Xiao; Ibarra, C.M.; Peiyi Zhao, “Design Asynchronous Circuits for Soft Error Tolerance,” Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on May 30 2007-June 1 2007 Page(s):1 – 5
[11]D. E. Muller, “Asynchronous logics and application to information processing,” Proc. Symp. Application of Switching Theory in Space Technology, H. Aiken and W. F. Main, Ed. , pp. 289-297, 1963.

[12]K.M. Chu and D.L. Pulfrey, “A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic,” IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 528–532, August, 1987.
[13]J.-L. Yang, E. Brunvand, “Self-timed circuits using DCVSL semi-bundled delay wrappers,” Proceedings of 2005 International Symposium on Intelligent Signal Processing and Communication Systems, 2005, 2005, pp.441-444.
[14]Muller, D. E.; Bartky, W. S. (1959), "A Theory of Asynchronous Circuits", Proc. Int'l Symp. Theory of Switching, Part 1 (Harvard Univ. Press): 204–243
[15]L.G. Heller, et al., “Cascode voltage switch logic: a differential CMOS logic family, ISSCC84 Digest, pp. 16–17, February, 1984.
[16]N. Kanopoulos and N. Vasanthavada, “Testing of Differential Cascode Voltage Switch (DCVS) Circuits,” IEEE J. Solid-State Circuits, vol. SC-25, no. 3, pp. 806–812, June, 1990.
[17]Charles, Cameron T.; Allstot, David J, “A buffered charge pump with zero charge sharing,” Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on 18-21 May 2008 Page(s):2633 – 2636.
[18]N. R. Mahapatra, A. Tareen, S.V. Garimella, “Comparison and analysis of delay elements“, In Proceedings of MWSCAS, Vol.2, pp.473-476, Aug.2002.
[19]M.G. Degrauwe, O.N. Leuthold, E.A. Vittoz, H.J. Oguey and A. Descombes, "CMOS Voltage Reference Using Lateral Bipolar Transistors", IEEE Journal of Solid State Circuits, 20(6), December 1985.
[20]K. G. Ashar "The method of estimating delay in switching circuits and the figure of merit of a switching transistor", IEEE Transactions on Electron Devices, pp.197 -506 1964
[21]Belkadi, M. ; Mouftah, H.T.“Modelling and test generation for MOS transmission gate stuck-open faults,”Circuits, Devices and Systems, IEE Proceedings G, Volume:139, Issue: 1, Page(s): 17-22, 1992
[22]Jung-Lin Yang and Chih-Wei Chao, "Post-Chip Adjustable Low Power Delay Element," 2007 VLSI Design/CAD Conference, 2007, Hualien, Taiwan
[23]Jung-Lin Yang, Wen-Yueh Lai, and Chen-Chia Yang, “An asymmetrical low-power tunable delay element,”In 2005 VLSI Design/CAD, Aug.2005
[24]Jung-Lin Yang, Chih-Wei Chao, “Ultra Low Power Delay Element with Post-Chip Adjustable Ability,”IEICE Trans. Fundamentals, Vol.E92-A, NO.12, pp.3381-3389, 2009.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關論文