In this thesis, a 0.18µm Bipolar CMOS DMOS (BCD) technology is simulated using Synopsys TCAD simulators. The process integration covers 5V to 60V operating voltage of some devices such as CMOS, Bipolar junction transistor (BJT), low-side N-channel LDMOS, high-side N-channel LDMOS and P-channel LDMOS with best in class specific-on resistance (Ron) for DMOS structures. Comparison of single resurf, double resurf and linear P-top is studied to get the best trade-off between breakdown voltage and Ron. The optimization of current gain of 20V BJT has been done by adjustment of emitter width and boron doping concentration of base with increasing of current gain up to ten times higher without significantly change the breakdown voltage.
Comparison between original and Silicon Controlled Rectifier (SCR) structure of a novel Shallow Trench Isolation (STI)-sided LDMOS with P-top layer is firstly presented. SCR structure can be used as a robust Electrostatic Discharge (ESD) protection device as its failure current (It2) is five times higher compared to original structure. This high It2 also results in optimizing of device width as the hot spot area is wider. The low holding voltage (Vh) of SCR structure is optimized by increasing the doping concentration of P-Body to minimize the risk of induced latch-up. The modification of surface doping concentration is the best way to increase the Vh as the crowded current of SCR structure is placed under the channel and source region while maintaining It2 below ESD thermal failure.

In this thesis, a 0.18µm Bipolar CMOS DMOS (BCD) technology is simulated using Synopsys TCAD simulators. The process integration covers 5V to 60V operating voltage of some devices such as CMOS, Bipolar junction transistor (BJT), low-side N-channel LDMOS, high-side N-channel LDMOS and P-channel LDMOS with best in class specific-on resistance (Ron) for DMOS structures. Comparison of single resurf, double resurf and linear P-top is studied to get the best trade-off between breakdown voltage and Ron. The optimization of current gain of 20V BJT has been done by adjustment of emitter width and boron doping concentration of base with increasing of current gain up to ten times higher without significantly change the breakdown voltage.
Comparison between original and Silicon Controlled Rectifier (SCR) structure of a novel Shallow Trench Isolation (STI)-sided LDMOS with P-top layer is firstly presented. SCR structure can be used as a robust Electrostatic Discharge (ESD) protection device as its failure current (It2) is five times higher compared to original structure. This high It2 also results in optimizing of device width as the hot spot area is wider. The low holding voltage (Vh) of SCR structure is optimized by increasing the doping concentration of P-Body to minimize the risk of induced latch-up. The modification of surface doping concentration is the best way to increase the Vh as the crowded current of SCR structure is placed under the channel and source region while maintaining It2 below ESD thermal failure.

DEDICATION i
ABSTRACT ii
ACKNOWLEGDE iii
TABLE OF CONTENTS iv
LIST OF FIGURES vi
LIST OF TABLES viii
Chapter 1 1
INTRODUCTION 1
1.1. Background 1
1.2. Motivation 4
1.3. Thesis Organization 5
Chapter 2 7
BIPOLAR CMOS DMOS PROCESS TECHNOLOGY AND ELECTROSTATIC DISCHARGE OVERVIEW 7
2.1, Bipolar CMOS DMOS Process Technology 7
2.1.1. Bipolar CMOS DMOS Fabrication Process 7
2.1.1.1. Lithography 9
2.1.1.2. Silicon Oxidation 10
2.1.1.3. Diffusion and Ion Implantation 11
2.1.1.4. Ion Implantation 11
2.1.1.5. Film Deposition 12
2.1.2. Electrical Behavior 12
2.1.2.1. Breakdown voltage 12
2.1.2.2. Specific-on Resistance (Ron) 13
2.1.2.3. Transconductance 14
2.1.2.4. Threshold Voltage 15
2.2. Electrostatic Discharge 17
2.2.1. Human Body Model 17
2.2.2. Protection Device 19
2.2.2.1. Gate grounded NMOS 20
2.2.2.2. Silicon Controlled Rectifier 20
Chapter 3 22
SIMULATION METHODOLOGY 22
3.1. Introduction of Simulation Platform 22
3.2. Process Simulation 23
3.3. Device Simulation 25
3.4. Human Body Model 26
Chapter 4 28
RESULTS AND DISCUSSIONS OF 5V to 60V 0.18µm BIPOLAR CMOS DMOS PROCESS TECHNOLOGY 28
4.1. 0.18µm Bipolar CMOS DMOS Process Technology 28
4.1.1. Process Flow Layout 28
4.1.2. TCAD Simulation Process 30
4.2. 0.18µm Bipolar CMOS DMOS Device Structures 33
4.2.1. CMOS 33
4.2.1.1. NMOS 34
4.2.1.2. PMOS 35
4.2.2. Bipolar Junction Transistor 36
4.2.2.1. NPN 37
4.2.2.2. PNP 39
4.2.3. LDMOS 41
4.2.3.1. Low-side N-channel LDMOS 41
4.2.3.2 High-side N-channel LDMOS 46
4.2.3.3. P-channel LDMOS 48
Chapter 5 51
HUMAN BODY MODEL TEST OF ELECTROSTATIC DISCHARGE PROTECTION DEVICE RESULTS AND DISSCUSSIONS 51
5.1. Device Structure 51
5.1.1 GGNMOS 51
5.1.2 Silicon Controlled Rectifier 53
5.2. Human Body Model Test 55
5.2.1. Optimization of Failure Current 55
5.2.2. Optimization of Device Width 57
5.2.3 Optimization of Holding Voltage 59
Chapter 6 62
CONCLUSION 62
REFERENCES 63

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