臺灣博碩士論文加值系統

非同步傳輸模式(ATM)擁有固定長度53 Bytes的細胞(Cell)特性，因此容易與其他不同需求的網路終端共享頻寬，也能夠簡化錯誤偵測機制，有效降低處理設備的負擔與提升傳輸品質，惟因LAN技術之中，乙太網路已然主流化，因此ATM系統一般會通過邊際交換器(Edge Switch)與Ethernet網路之交換器連接，進行通過細胞和封包間的轉換，並依LAN類型做訊框化，為終端用戶服務，達到容易、快速與方便的功能。
本系統晶片係以硬體描述語言Verilog實現ATM細胞與Ethernet訊框間之UTOPIA轉換介面，並整合具有路由分類功能之封包處理器，使其成為具邊際交換器功能之連結層交換器；Ethernet封包採用IEEE標準訊框格式，並建立於MII協定上，以得到媒介獨立與高擴充性的優點，該連結層交換器具有傳送與接收端，解析傳送與接收到的封包，將各自之來源與目的位址儲存在相同交換表，使其達到雙向資料過濾與轉送功能，並使用異步FIFO連結UTOPIA的傳送與接收介面，以確保資料正確性及設計彈性，最後以現場可編程邏輯閘陣列開發版(Altera DE3)驗證無誤後，使用TSMC之0.18-μm製程並經過Synthesis、DFT、APR、DRC/LVS等流程製作出專用晶片(ASIC)，其邏輯閘數(Gate Count)約為128000，動態功率約為165mW，錯誤涵蓋率約為96%。

ATM (Asynchronous Transfer Mode) cell inherits with a fixed length of 53 bytes. This feature intends to share the bandwidth with other network terminals which performs with different applications. Also, ATM has the ability to simplify the fault detection scheme, to effectively lower the encumbrance; and to promote the quality of transmission. Besides, Ethernet becomes the main stream among the technology of LAN (Local Area Network). And that ATM is a convenient network to consist with the LAN. Generally, the ATM connects the Ethernet Switch through the Edge Switch, and it needs a transformed interface between the Cell and the Packet to frame ATM cell into Ethernet packet based on the types of the LAN which offers the service to the client.

The UTOPIA(Universal Test and Operations PHY Interface for ATM),which is the transformed interface of the ATM Cell and the Ethernet packet, is designed with Verilog hardware describe language and is integrated with the packet processing unit with the function of routing and classification and with the Link Layer Switch with the function of Edge Switch. The Ethernet Packet presents with IEEE standard frame ,and it builds up on the environment of MII (Media Independent Interface) in order to acquire the benefit of high flexibility and high expandability. The Link Layer Switch include the transmitter and receiver units which can analyze the transmitted and received packets; and It also stores the MAC addresses with different sources according to the established lookup table to filter and transmit the two-way information. The Edge Switch uses an asynchronous FIFO (First In First Out Queue) to make sure the validity and flexibility of the information by connecting the UTOPIA module. Finally, the Altera DE3 of FPGA (Field Programmable Gate Array) is used to verify the designed function; and the TSMC 0.18-μm CMOS technology is selected to implement the ASIC by passing through the procedure of Synthesis、DFT(Design For Testability)、APR(Auto Place and Route)、DRC(Design Rule Check)、LVS(Layout Versus Schematic). After simulation, the proposed ASIC performs with the gate count of 128,000, the dynamic power of 165mW, and the fault coverage is 96% at the power supply of 1.8V and operating frequency of 50 MHZ.

摘 要 I
ABSTRACT III
誌 謝 V
目 錄 VI
表目錄 VIII
圖目錄 IX
第一章 緒論 1
1.1 研究動機 1
1.2 論文組織 3
第二章 網路協定與架構 4
2.1區域網路與骨幹網路 4
2.1.1網際網路服務供應者 5
2.1.2區域網路 6
2.1.3廣域網路 6
2.1.4非同步傳輸模式 7
2.2網際網路協定堆疊 9
2.3高速乙太網路 12
2.4交換器內部結構 13
2.5網路延遲 15
2.6排班機制 16
2.7擁塞管理 19
2.8非同步佇列 22
第三章 系統架構設計 27
3.1 UTOPIA 27
3.1.1傳送端電路 .27
3.1.2接收端電路 28
3.2交換器 29
3.3全架構 33
3.4非同步佇列 36
3.5傳送控制 37
3.6接收控制 40
第四章 模擬與電路驗證 42
4.1 UTOPIA 42
4.2發送端 43
4.3接收端 45
4.4邏輯分析儀 47
4.5處理時間 50
第五章 數位積體電路流程 51
5.1介紹 51
5.2電路合成與電路可測性 52
5.3自動佈局與繞線 53
5.4設計規則與電路比對 56
第六章 結論與未來工作 57
6.1結論 57
6.1未來工作 58
參考文獻 59

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