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研究生:蘇哲彥
研究生(外文):Je-Yan Su
論文名稱:應用多層級平面規劃於三維超大型積體電路
論文名稱(外文):Realization of Multilevel-floorplanning on 3D-VLSI
指導教授:方志鵬方志鵬引用關係
指導教授(外文):Jyh-Perng Fang
口試委員:饒建奇李宗演
口試委員(外文):Jiann-Chyi RauTrong-Yen Lee
口試日期:2013-06-21
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電機工程系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:31
中文關鍵詞:多層級平面規劃矽穿孔
外文關鍵詞:MultilevelfloorplanTSV
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技術不斷的更新,晶片內所容納的模組數量極為龐大。複雜的電路容易造成繞線過長甚或失敗,因此近年來二維平面規劃逐漸轉為三維樓層規劃。現有的文獻顯示幾乎所有的三維樓層規劃都將各層視為一個平坦的平面(flat plane),然後對各層獨立進行二維的平面規劃。這樣的作法會喪失層間的資訊,導致同一個網列中的模組卻分置於上下層的不同角落。
本研究使用變種的多層級平面規劃(layer-aware multilevel floorplanning,簡稱LAML),此方法用K-L分割演算法進行分層,再用同一個演算法對各層進行細化(uncorsening),細化時會盡量將不同層中屬於同一網列的模組放至較接近的區域中,再對個別小集合做平面規劃,但我們不作完全粗化(corsening)。最後則是採用漸近式掃描法根據空白區域決定候選的矽穿孔(through-silicon vias,TSVs),再透過配對方式篩選並保留較適合的TSV。實驗結果顯示多層級平面規劃配合漸近式掃描法及TSV的配對可以有效加速計算並縮短線長。

Technology is updated continuously. The number of the modules on the chip was complicated. It intends to influence the wirelength and make the design fail. Thus, the 2D planar architecture gradually moved into 3D stack architecture in recent years. Most of the existing floorplanner formulated each layer in the 3D stack into a flat plane and floorplan each layer independently. It would lose the information between layers, and let the relation modules be placed on different corners.
Instead, we used an improved layer-aware multilevel floorplanning approach. It partitioned the modules into different layers by K-L algorithm, then used the same algorithm to perform uncorsening for the each layer. During uncorsening phase, modules of the same TSV’s matching will be put closely, even if they belongs to different layers. Then floorplan each partition is floorplanned independently. In our approach, corsening is not necessary. After floorplanning, we use an incremental scanning method to scan possible blank area to decide candidate TSVs, and then apply a TSV’s matching approach retain suitable TSVs from candidate TSVs. Experimental results show that multi-level floorplan with incremental scanning method and TSV’s matching can effectively speed up the calculation and shorten the wirelength.

摘 要 I
Abstract II
誌 謝 III
目 錄 IV
表目錄 VI
圖目錄 VII
第一章緒論 1
1.1研究背景 1
1.2研究動機與目的 1
1.3論文架構 2
第二章相關文獻 3
2.1 KL (Kernighan-Lin)演算法 3
2.2多層級平面規劃(Multilevel Floorplanning) 4
2.3模擬退火(Simulated Annealing-SA)法 5
2.4序列對(Sequence Pair)表示法 6
2.5 TSV (Through-silicon via) 7
2.6 Layer Assignment Partitioning 8
2.7 線長計算 9
第三章研究方法 10
3.1概述 10
3.2分層 11
3.2.1 KL切割與模組面積調整 11
3.2.2層級面積大小 13
3.2.3層級順序 14
3.3平面分割與規劃 15
3.3.1分割轉換 16
3.3.2分割層級 16
3.3.3適合放置區塊 17
3.3.4單一層級粗化 19
3.4 TSV放置與篩選 20
3.4.1漸進式掃描法 20
3.4.2 配對法 21
第四章實驗結果 24
4.1實驗環境 24
4.2實驗結果 24
第五章結論與未來展望 29
5.1結論 29
5.2未來展望 29
參考文獻 30


1.D. Noice and V. Gerousis. (2010), Physical design implementation for 3-D IC :Methodology and tools. Invited talk at Int. Symp. Phys. Design [Online], Available: http://www.ispd.cc/slides/slides10/4_02.pdf.
2.Tung-Chieh Chen, Yao-Wen Chang and Shyh-Chang Lin, “IMF: Interconnect-Driven Multilevel Floorplanning for Large-Scale Building-Module Designs,” IEEE/ACM International Conference on Computer-Aided Design, 2005. ICCAD-2005, 2005,pp.159-164.
3.X. Tang, R. Tian, D.F. Wong, "Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 20,no. 12, December 2001,pp.1406-1413.
4.Ya-Shih Huang, Yang-Hsiang Liu and Juinn-Dar Huang, “Layer-Aware Design Partitioning for Vertical Interconnect Minimization,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2011, 2011,pp.144-149.
5.G. Karipis and V. Kumar “Multilevel k-way Hypergraph Partitioning” VLSI Des., vol. 11,no. 3, 2000, pp.285-300.
6.Cha-Ru Li, Wai-Kei Mak and Ting-Chi Wang, “Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013,pp.523-532.
7.S. N. Adya and I. L. Markov, “Fixed-outline floorplanning : Enabling hierarchical design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, December 2003, pp.1120–1135.
8.Ming-Chao Tsai, Ting-Chi Wang and TingTing Hwang, “Through-Silicon Via Planning in 3-D Floorplanning,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, December 2011, pp.1448–1457.
9.Dae Hyun Kim, R. O. Topaloglu, and Sung Kyu Lim“Block-level 3D IC design with through-silicon-via planning,” Automation Conference (ASP-DAC), Asia and South Pacific, 2012, pp.335–340.
10.Baofang Chang, Wu Jigang and, Srikanthan T and Lian Li, “Fast evaluation-based algorithm for fixed-outline floorplanning,” International Conference on Computer Engineering and Technology (ICCET), 2010, pp.v2-81-v2-85.


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