(3.235.41.241) 您好!臺灣時間:2021/04/11 21:34
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:朱劍英
研究生(外文):Chien-Ying Chu
論文名稱:電池保護積體電路測試系統之實務研究
論文名稱(外文):The Practical Research of Battery Protection Integrated Circuit Testing System
指導教授:黃育賢
口試委員:李文達郭建宏李宗演陳建中
口試日期:2013-01-21
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電資碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:73
中文關鍵詞:ATE半導體測試IC測試電池保護測試系統
外文關鍵詞:ATESemiconductor TestIC TestBattery ProtectionTest System
相關次數:
  • 被引用被引用:1
  • 點閱點閱:537
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:58
  • 收藏至我的研究室書目清單書目收藏:0
近年來,類比電源半導體開發公司都需面對快速研發產品及提升投資獲利等基本問題,還需面臨如何降低半導體測試成本、縮短開發測試模組時間及提高驗證準確度等難題。因此,產業界都會採用ATE(Automatic Test Equipment)專業半導體測試系統平台進行IC測試工程開發,來解決上述難題。半導體測試工程雖然在整個半導體製程中屬於後端工程階段,但此階段為決定產品良率及品質的重要關鍵,其目的可降低封裝成本損失及確保產品符合客戶端規範。
本論文運用ASL1000半導體測試機,搭配電池保護IC產品,針對測試開發流程與IC功能測試方法進行討論,包括基本直流測試、過充檢測電壓與檢測時間測試、輸入阻抗測試、臨界值測試及輸入與輸出電流測試等驗證設計。結合實務案例設計開發,說明測試程式的撰寫、負載電路板及待測物電路板的設計製作及相關注意事項,至最後測試計劃的擬定及測試工程的實現與驗證。


In recent years, the analog power semiconductor development companies are required to face some basic questions, like faster product development and enhancement of the investment profit. Otherwise, there are some challenges, such as how to reduce the cost of semiconductor test, shorten development time and improve the verification accuracy. Therefore, industry adopts ATE (Automatic Test Equipment) the professional semiconductor testing system platform to develop the IC test engineering. The semiconductor test engineering in the semiconductor manufacturing process belongs to the back-end project phase, but this phase is important for yield rate and quality. It can reduce the packaging costs and make sure that the products conform to the specifications of the client. This thesis uses ASL1000 test machine with battery protection IC products to discuss the IC function test and the test development process, including basic DC test detection time, overcharge detection voltage and critical values of input impedance test, and test validation of input and output current design.
This thesis includes the design and development case, interpreting the development of the test program, the design and the implementation of the load circuit board and the DUT circuit board, and the related considerations. At last, we draft the test plan, accomplish and verify the test engineering.


中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 導論 1
1.1 研究動機與目的 1
1.2 論文架構 1
第二章 測試開發程序 3
2.1 後端生產流程 3
2.2 自動化測試 5
2.2.1 半導體專業測試機 6
2.2.2 晶片探測機 7
2.2.3 機械式自動操作設備 7
2.3 測試裝置 8
2.3.1 負載電路板 8
2.3.2 待測物電路板 9
2.4 測試程式 11
第三章 半導體測試機概述及基本IC直流測試 14
3.1 ASL1000測試機系統 14
3.1.1 硬體簡介 14
3.1.2 專業儀器板卡 19
3.1.3 軟體系統簡介 20
3.2 基本IC直流測試 23
3.2.1 開路與短路量測法 23
3.2.2 電源腳的開路與短路量測法 28
3.2.3 輸入腳漏電流量測法 30
3.2.4 輸出腳漏流量測法 32
第四章 電池保謢IC主要功能與參數測試 34
4.1 測試開發範例產品:電池保謢IC 34
4.2 過充電與過放電檢測電壓及延遲時間測試 36
4.3 過電流檢測電壓及延遲時間測試 39
4.4 向0V電池充電測試 42
4.5 輸入阻抗測試 43
4.6 CTL端子位準測試 45
4.7 輸入電流測試 45
4.8 輸出電流測試 47
第五章 實驗結果 48
5.1 專案測試開發流程 48
5.2 常見問題解決與改善方式 63
5.2.1 測試時間過長問題 63
5.2.2 時間差量測異常問題 64
第六章 結論與未來研究 70
參考文獻 71

[1]K. Kulovic, S. Maltabas, and M. Margala, “Design-for-Test Methodologies for Current Tests in Analog/Mixed-Signal Power SOCs,” in Proc. of IEEE International Midwest Symposium on Circuits and Systems, 2012, pp. 1056-1059.
[2]C. Y. Chang, C. Y. Hsiao, K. J. Lee and A. P. Su, “Transaction Level Modeling and Design Space Exploration for SOC Test Architectures,” in Proc. of Asian Test Symposium(ATS), 2009, pp. 200-205.
[3]K. J. Lee, C. Y. Chang, A. Su, and S. Y. Liang, “A unified test and debug platform for SOC design,” in Proc. of International Conference on ASIC, 2009, pp. 577-580.
[4]Z. Quming, and K. J. Balakrishnan, “Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling,” in Proc. of Design on Automation and Test in Europe Conference and Exhibition, 2007, pp. 1-6.
[5]陳景聰,積體電路測試之實務分析與研究,碩士論文,私立長庚大學電機工程研究所,桃園,2007。
[6]吳明隆,單晶片系統測試平台之效能分析與增進,碩士論文,國立成功大學電機工程學系,台南,2005。
[7]J. L. Orlet, “Test system consolidation,” in Proc. of IEEE AUTOTESTCON, 2012, pp. 265-268.
[8]P. Gilenberg, “What to do when your automated test equipment and Unit Under Test are out of reach?,” in Proc. of IEEE AUTOTESTCON, 2012, pp. 161-165.
[9]W. Xiaoqing, “VLSI testing and test power,” in Proc. of International Green Computing Conference and Workshops(IGCC), 2011, pp. 1-6.
[10]蔚華科技,http://www.spirox.com.tw/。
[11]M. Lockhart, L. Clabon, C. Lott, and M. James, “Automated Battery Tester Data Acquisition System Using LabVIEW,” IEEE Region 5 Conference, 2008, pp. 1-6.
[12]R. Singh, Y. Audet, Y. Gagnon, and Y. Savaria, “Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier,” in Proc. of International Symposium on Circuits and Systems, 2007, pp. 709-712.
[13]S. C. Lee, S. Demidenko, K. H. Lee, “IC Handler Throughput Evaluation for Test Process Optimization,” in Proc. of Instrumentation and Measurement Technology Conference Proceedings (IMTC), 2007, pp. 1-6.
[14]D. Zaleski, R. Zielonko, and B. Bartosinski, “Application of Complementary Signals in Built-In Self Testers for Mixed-Signal Embedded Electronic Systems,” IEEE Transactions on Instrumentation and Measurement, 2010, pp. 345-352.
[15]T. H. Moita, C. B. Almeida, and M. B. Dos Santos, “DETECTOR: Design and test characterization of mixed-signal power cores,” in Proc. of International Mixed-Signals on Sensors and Systems Test Workshop (IMS3TW), 2010, pp. 1-6.
[16]美達科技,http://www.trade-taiwan.org/WebSiteTemp/a4.asp?v_id=13115906。
[17]德律科技,http://www.tri.com.tw/cht/career.aspx。
[18]F. Wang, R. Cheng, and X. Li, “MEMS Vertical Probe Cards With Ultra Densely Arrayed Metal Probes for Wafer-Level IC Testing,” Journal of Microelectromechanical Systems, 2009, pp. 933-941.
[19]S. M. Low, M. Phoon, A. Suffian, and Johan, “An Experimental Result on the Effect of Bypass Capacitance in Load Board for Semiconductor’s Speed Testing,” in Proc. of Electronics Packaging Technology Conference (EPTC), 2008, pp. 1196-1201.
[20]S. C. Lee, S. Demidenko, K. H. Lee, “IC Handler Throughput Evaluation for Test Process Optimization,” in Proc. of Instrumentation and Measurement Technology Conference Proceedings (IMTC), 2007, pp. 1-6.
[21]Y. G. Yabut, F. F. Galauran, M. C. Dator, and J. D. Encarnado, “Device Under Test (DUT) Socket Conversion to Improve Analog Loadboard Performance Efficiency,” in Proc. of International Conference on Electronics Manufacturing and Technology, 2006, pp. 492-495.
[22]台灣普羅卡科技,http://www.taiwanpage.com.tw/co.cfm?id=7741。
[23]白安鵬,半導體積體電路測試概論,Blogger,桃園,2008。
[24]M. Richter, and K. Chakrabarty, “Test pin count reduction for NoC-based Test delivery in multicore SOCs,” in Proc. of Design on Automation and Test in Europe Conference and Exhibition, 2012, pp. 787-792.
[25]Y. Feng, and X. Qiang, “SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects,” in Proc. of International Test Conference (ITC), 2008, pp. 1-9.
[26]A. Das, U. Kocabas, A. Sadeghi, and I. Verbauwhede, “PUF-based secure test wrapper design for cryptographic SoC testing,” in Proc. of Design on Automation and Test in Europe Conference and Exhibition, 2012, pp. 866-869.
[27]楊濬宇,無線測試機台之封套合成及測試程式自動產生器,碩士論文,國立清華大學電機工程學系,新竹,2008。
[28]L. Sok, “Integration of mobile devices and ATE systems,” in Proc. of IEEE AUTOTESTCON, 2012, pp. 153-156.
[29]陳育興,多重測試對最佳測試良率、品質與測試機準度之研究,碩士論文,私立中華大學電機工程學系,新竹,2000。
[30]M. Richter, and K. Chakrabarty, “Test pin count reduction for NoC-based Test delivery in multicore SOCs,” in Proc. of Design on Automation and Test in Europe Conference and Exhibition, 2012, pp. 787-792.
[31]S. D. Dasnurkar, and J. A. Abraham, “Frequency-Independent Parametric Built in Test Solution for PLLs with Low Speed Test Resources,” in Proc. of International Mixed-Signals on Sensors and Systems Test Workshop (IMS3TW), 2012, pp. 73-78.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔