一個數位輸出的酸鹼值感測系統包括了前端的讀出電路、溫度補償電路，以及後端的類比數位轉換器。本文探討酸鹼值感測系統前端部分的設計並以八位元雙斜率積分式類比數位轉換器實現完整架構。系統前端部分以低功率的CMOS臨界電壓來感測電路對酸鹼的變化，並使用溫度補償電路產生負溫度係數來補償讀出電路的溫度效應。電路模擬是使用3.3 伏特及台積電公司的 0.35um CMOS 的標準製程參數並用 HSPICE軟體完成模擬分析。
此酸鹼值感測器在0℃至100℃的溫度範圍內，模擬顯示能產生一個不受溫度影響並正比於酸鹼值的感測輸出電壓，其溫度係數為0.03mV⁄℃，靈敏度為46.88mV⁄pH。八位元雙斜率積分類比數位轉換器其在pH1到pH10的輸出值為15至196，適用於酸鹼值感測系統。

A pH value sensing system with digital outputs consists of readout circuit, a temperature compensation circuit in the front end and an analog-to-digital converter (ADC) in the back end. In this thesis, a low power consumption threshold-voltage based readout circuit is presented, and temperature compensation circuit is achieved by using a negative temperature coefficient generator to compensate the readout circuit. In addition, an 8-bit dual slope ADC is designed to convert the output of the pH sensor to a digital code. The simulation results obtained from HSPICE using a standard TSMC 0.35μm CMOS models and 3.3V power supply are presented in the thesis.
This sensor is almost insensitive to the temperature and is linear dependent to pH value. The simulation result shows that the voltage output of the sensor has the temperature coefficient of 0.03mV⁄℃ from 0℃ to 100℃, and sensitivity is 46.88mV⁄pH. The 8-bit dual slope ADC output code is from 15 to 196 for pH1 to pH10, which can meet the requirement of the pH value sensing system.

ACKNOWLEDGEMENT i
ENGLISH ABSTRACT ii
CHINESE ABSTRACT iii
CONTENTS iv
LIST OF FIGURES viii
LIST OF TABLES xi
CHAPTER 1 Introduction 1
1.1 Thesis Motivation 1
1.2 Thesis Organization 2
CHAPTER 2 ISFET Sensing Principle 3
2.1 General Background 3
2.2 ISFET Sensor Characteristic 4
2.3 The Undesirable Effects of ISFET 7
2.3.1 Light Effects 7
2.3.2 Noise Effects 7
2.3.3 Temperature Effects 7
2.3.4 Time-variant Effects 9
2.3.5 Hysteresis Effects 10
2.3.6 Flow Rate Effects 10
2.3.7 Body Effect 10
2.3.8 Life Cycle Effect 11
2.4 EGFET 11
CHAPTER 3 The Circuit Operation 12
3.1 ISFET Based PH Meter 12
3.1.1 Readout Circuit Related Research 13
3.1.2 Low Power Consumption Readout Circuit 16
3.1.3 The Adjustment Circuit 19
3.2 Design of Temperature Compensation Circuit Architecture 20
3.2.1 Temperature Dependence of Threshold Voltage 20
3.2.2 Threshold Voltage Extractor Theory 23
3.2.3 Temperature Compensation Circuit Architecture 25
3.2.4 Rail-to-rail Op-amp Design 27
3.2.5 Bandgap Voltage Generator Circuit 32
3.2.6 The Temperature Compensation Circuit 34
CHAPTER 4 A/D Converter Architectures 36
4.1 Introduction to Analog-to-digital Converter 36
4.2 Comparator 37
4.3 Design of Dual Slope ADC 38
4.3.1 Operation of the Single Slope ADC 38
4.3.2 Operation of the Dual Slope ADC 39
4.4 Design Specifications 40
4.4.1 Specification of Two Stage Op-amp 40
4.4.1.1 Design Procedure 41
4.4.1.2 Op-amp Simulation Result 44
4.4.2 Integrator 44
4.4.3 Comparator 45
4.4.4 Control Logic 45
4.4.5 8-bit Counter 46
CHAPTER 5 Simulation Results 47
5.1 The Pre-simulation Results of the 8-bit CMOS PH-to-digital Converter 47
5.2 The Post-simulation Results of the 8-bit CMOS PH-to-digital Converter 52
5.3 Chip Layout for the EGFET PH Sensor 54
5.4 Measurement Setup 55
5.5 Measurement Results 55
CHAPTER 6 Conclusions 57
6.1 Conclusion 57
6.2 Future Work 57
REFERENCES 58

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