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研究生:蔡政諭
研究生(外文):Zheng-Yu Cai
論文名稱:只用金氧半場效電晶 體次臨界洩漏壓抑低電壓完全差動互補金氧半交換電容放大器之研究
論文名稱(外文):The research on MOSFET-Only Subthreshold-Leakage Suppressed Low-Voltage Fully Differential CMOS Switched-Capacitor Amplifier
指導教授:李蒼松
指導教授(外文):Cang-Song Li
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與光電工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:72
中文關鍵詞:只用金氧半場效電晶體次臨界洩漏壓抑低電壓交換電容放大器
外文關鍵詞:switched-capacitor amplifierCMOSlow-voltagesubthreshold-leakageMOSFET-only
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本論文提出一0.6V只用金氧半場效電晶體互補金氧半完全差動次臨界洩漏壓抑低電壓交換電容放大器,並採用類比T-開關 (Analog T-switch )與標凖TSMC 0.18um CMOS製程。本電路使用了基板偏壓(substrate-biased)的MOSFETs,工作在空乏區 (depletion region) 以用來作為電容使用。詳細的電路在本文中被清楚的描述。最後的模擬結果及實體佈局結果證實了本設計的可行性,並滿足了本設計的需求。
A 0.6-V MOSFET-only subthreshold-leakage suppressed CMOS fully differential switched-capacitor amplifier using analog T-switch scheme in a standard 0.18μm CMOS technology is presented. The circuit uses
substrate-biased MOSFETs in depletion region as capacitors linearized by compensation technique. The circuit design of major building blocks is described. The performance of this circuit is demonstrated by simulation results. The simulation results confirm the capability of compensated depletion-mode MOS capacitors and analog T-switch scheme to fulfill circuit
requirements.
中文摘要................................................ i
英文摘要................................................. ii
誌謝.................................................... iii
目錄....................................................... iv
表目錄...................................................... vi
圖目錄................................................. vii

第一章 緒論.............................................. 1
1.1研究動機......................................... 1
1.2研究目標........................................ 3
1.3論文架構...................................... 3
第二章 交換電容電路之概論................ 4
2.1交換電容電路之介紹............................... 4
2.2交換電容電路開關的設計及考量……………………….. 5
2.2.1開關的電荷注入效應 (Charge Injection)………… 5
2.2.2開關的時脈滲透現象 (Clock Feedthrough)… 7
2.2.3開關的導通電阻…………………………… 8
2.3 MIM電容(metal-insulator-metal capacitor)………… 10
2.4時脈產生器的設計及考量………………………… 13
2.4.1非重疊的時脈訊號 (nonoverlapping clock)…… 13
2.4.2底板取樣 (Bottom plate sampling)……………… 13
2.5運算放大器的設計及考量……………………………… 15
第三章 補償式金氧半電容(COMPENSATED MOS CAPACITORS) ………… 20
3.1 金氧半電容(MOS CAPACITORS)………………………… 20
3.2 串聯補償空乏模式金氧半電容(Series Compensated Depletion-Mode MOS Capacitors, SCDM-MOSCAP)………… 21
3.3 並聯補償空乏模式金氧半電容(Parallel Compensated Depletion-Mode MOS Capacitors, PCDM-MOSCAP)………… 23
第四章 交換電容電路的設計及模擬…………………………… 26
4.1全電路工作原理及輸出結果……………………… 28
4.1.1只用金氧半場效電晶 體次臨界洩漏壓抑低電壓
完全差動互補金氧半交換電容放大器 28
4.1.2全電路輸出結果………………………………… 32
4.2低電壓運算放大器電路的架構……………………… 34
4.2.1 典型運算放大器的比較…………………… 34
4.2.2低電壓運算放大器的電路技巧與比較…………… 35
4.2.3 本論文運算放大器架構及共模回授電路………… 37
4.2.4運算放大器特性模擬……………………………… 39
4.3時脈產生電路的架構……………………………………… 41
第五章 交換電容電路實體佈局及佈局後模擬…………………… 42
5.1基本佈局考量…………………………………………… 42
5.2類比元件佈局考量……………………………………… 44
5.3實際電路佈局………………………………………… 45
5.4佈局後模擬結果………………………………………… 48
5.5測試考量………………………………………………… 63
第六章 結論及未來研究方向………………………………64
6.1結論…………………………………………………… 64
6.2未來研究方向…………………………………………… 65
參考文獻……………………………………………………………… 66
[1] K. Martin, L. Ozcolak, Y. S. Lee, and G. C. Temes, “A differential switched-capacitor amplifier,” IEEE J. Solid-State Circuits, vol. 22, pp. 104-106, Feb. 1987.
[2] J. W. Yang and K. W. Martin, “High-resolution low-power D/A converter,” IEEE J. Solid-State Circuits, vol. 24, pp. 1458-1461, Oct. 1989.
[3] J. Crols and M. Steyaert, “Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltage,” IEEE J. Solid-State Circuits, vol. 29, pp. 936-942, Aug. 1994.
[4]H. Yoshizawa, Y. Huang, P. F. Ferguson, Jr., and G. C. Temes, “MOSFET-only switched-capacitor circuits in digital CMOS technology,” IEEE J. Solid-State Circuits, vol. 34, pp. 734-747, June 1999.
[5] T, S. Lee and C. C. Lu, “Two 1-V fully differential CMOS switched-capacitor amplifiers,” Circuits, Systems and Signal Processing, Vol. 29, No.2, pp. 195-207, April 2010.
[6] K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, “Managing subthreshold leakage in charge-based analog circuits with low- transistors by analog T-switch (AT-switch) and super cut-off CMOS (SCCMOS),” IEEE J. Solid-State Circuits, vol. 41, pp. 859-867, April 2006.
[7] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanism and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proc. IEEE, vol. 91, no. 2, pp.305-327, Feb. 2003.
[8] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, New York: Cambridge Univ. Press, 1998.
[9] H. Roh, H. Kim, Y. Choi., J. Roh, Y.-G. Kim, and J.-K. Kwon, “A 0.6-V delta-sigma modulator with subthreshold-leakage suppression switches,” IEEE Trans. on Circuits and Systems-II, vol. 56, pp. 825-829, Nov. 2009.
[10]T. S. Lee and C. C. Lu,” 0.6-V subthreshold-leakage suppressed fully differential CMOS switched–capacitor amplifier,” Analog Integrated Circuits and Signal Processing, Vol. 74, No.2, February, pp. 409-416, 2013.
[11] T. Tille, J. Sauebrey, and D. Schmitt-Landsiedel, “A 1.8V MOSFET-only modulator using substrate biased depletion-mode MOS capacitors in series compensation,” IEEE J. Solid-State Circuits, vol. 36, pp. 1041-1047, July 2001.
[12] J. Sauebrey, T. Tille, D. Schmitt-Landsiedel, and R. Thewes,” A 0.7V MOSFET-only Switched–opamp modulator in standard digital CMOS technology,” IEEE J. Solid-State Circuits, vol. 37, pp. 1662-1669, December 2002
[13] T. Tille, J. Sauebrey, M. Mauthe, and D. Schmitt-Landsiedel, “Design of low-voltage MOSFET-only modulator in standard digital CMOS technology,” IEEE Trans. on Circuits and Systems-I, vol. 51, no. 1, pp. 96-109, January 2004.
[14] H. Matsumoto and K. Watanabe, “Spike-free switched-capacitor circuit,” Electron. Lett., vol. 23, no. 8, pp. 428-429, April 1987.
[15] M. Waltari and K. Halonen, “Fully differential switched opamp with enhanced common-mode feedback,” Electron. Lett., vol. 34, no. 23, pp. 2181-2182, Nov. 1998.
[16]D. Garrity and P. Rakers, “Common-mode output sensing circuit,” U.S. Patent 5 894 284, April 13, 1999.
[17] O. Choksi and L. R. Carley, “Analysis of switched-capacitor common-mode feedback circuit, “IEEE Trans. on Circuits and Systems-II, vol. 50, pp. 906-917, Dec. 2003.
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