跳到主要內容

臺灣博碩士論文加值系統

(44.213.60.33) 您好!臺灣時間:2024/07/20 05:28
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:洪子閔
研究生(外文):Zim-min Hong
論文名稱:全數位高速寬頻域線性循環二進制偵測脈波寬度鎖定迴路
論文名稱(外文):All-Digital High Speed Wide-Range Linear Cyclic Binary Detection Pulse Width Locked Loops
指導教授:楊博惠
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與光電工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:109
中文關鍵詞:脈波寬度鎖定迴路延遲線工作週期控制
外文關鍵詞:delay linepulse width locked loopsduty cycle control
相關次數:
  • 被引用被引用:1
  • 點閱點閱:184
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在高速系統級晶片裡,時脈訊號會因為內部電晶體的製程、溫度、電壓等變 異造成時脈訊號的失真,而導致電路效能無法提升甚至操作錯誤。可見得時脈信 號中的脈波寬度的穩定性,在電路中要求也越來越高,如在管線系統、高速的動 態電路、雙倍取樣的系統中或需要正負緣觸發電路都需要有穩定的脈波寬度。因 此,一個穩定的工作週期鎖定電路,是現今SOC重要的子系統之一。

本論文提出一個新型的全數位式脈波寬度控制迴路,使用線性循環式延遲線 應用於本論文所提出的線性循環式二進制脈波偵測器與脈波產生機制,讓電路不 須增加延遲線級數即可將操作頻率降低。

本論文所提出的線性循環式二進制脈波偵測器,延遲線設計僅為十六級,以 線性循環技術,及特別安排的二進制的升冪排列方式。讓此本論文提出的脈寬偵 測電路,可以線性連續偵測,可快速將週期碼與脈寬碼偵測量化,達到偵測量化 只需三個時脈週期完成。在本論文的脈波產生架構為兩階段延遲線,當操作於高 頻段時,關閉循環式延遲線,只由低四位元控制的多工器延遲線產生脈寬。當操 作於低頻時,開啟循環式延遲線,以線性二進制循環的方式,產生低頻輸出脈寬 所需的大量延遲時間。在本論文為補償電路不平衡的延遲誤差,提出以自我校準 技巧,經由加減法器將脈寬碼矯正,技巧只須迴授偵測矯正兩次,即可達到鎖定 輸出時脈。在本論文所提出的新型架構效能,使用TSMC 90nm CMOS 模擬,具 有25%、50%、75%三種輸出鎖定脈寬可供使用,操作頻寬為100MHz∼3GHz,鎖 定時間為25時脈週期。
In the high-speed system chip inside, because the internal clock signal transistor manufacturing process, temperature, voltage variations caused by clock signal distortion, and even circuit performance can not be improved or operational error. These show the clock signal pulsewidth stability, in the circuit requirements are also increasing, as in piping systems, high-speed dynamic circuits, double sampling system or need negative edge trigger circuit needs to have stable a pulsewidth. Therefore, a stable working cycle lockout circuit is now an important issue.

This thesis presents a new fully digital pulsewidth control circuit, using a linear cyclic delay line used in this thesis proposed a linear cyclic binary pulse detector and pulse generator mechanism so that the circuit does not need to increase the delay line progression to the low operational frequency state.

The proposed linear cyclic binary pulse detectors, delay line design is only sixteen stage, in a linear cycle technology, and special arrangements are arranged in ascending binary mode. The proposed pulse detection circuit that can detect linear continuous, rapid quantized pulse code and cycle detection code detect quantitative takes only three clock cycles to complete. In this thesis, the pulse generator for the two-stage delay line architecture, when operated at high frequency band, close the loop delay line, only four bit from low to generate pulsewidth controlled delay line multiplexer. When operating in low frequencies, the open loop delay line, a linear binary cycle, generate a lot of low-frequency output pulse required delay time. In this thesis is unbalanced delay error compensation circuit is proposed in order to self-calibration techniques, through the pulse code subtractor correction techniques detect only feedback correction twice to reach locked output clock. In this thesis, the performance of the proposed new architecture using TSMC 90nm CMOS analog, with 25%, 50%, 75% three output locked pulse width is available, the operating bandwidth of 100MHz ∼ 3GHz, lock time of 25 clock cycles.
中文摘要.....................................i
英文摘要......................................ii
誌謝 .........................................iii
目錄 ..................................... iv
表目錄 ..................................... vii
圖目錄 ..................................... viii

一、緒論 ..................................... 1
1.1 研究動機..................................... 2
1.3 論文架構 ..................................... 2

二、傳統脈波寬度鎖定迴路設計 ..................................... 4
2.1 數位類比混合式脈波寬度鎖定迴路 ..................................... 4
2.2 全數位式脈波寬度鎖定迴路 ..................................... 5
2.2.1 全數位延遲鎖定迴路之輸入非50%工作週期快速鎖定 ..... 5
2.2.2 全數位可調整工作週期脈波寬度控制迴路 ........................... 7
2.2.3 全數位脈波寬度控制迴路 ...................................... 9
2.2.4 全數位半工作週期矯正電路 ..................................... 10
2.2.5 全數位工作週期矯正電路 ...................................... 10
2.3 文獻效能分析 ..................................... 11

三、新型脈波寬度鎖定迴路之設計概念及電路動作 ................ 13
3.1 傳統量測量化電路 ..................................... 13
3.2 傳統循環取樣式脈波偵測器與傳統循環式脈波寬度鎖定迴路電路 ......... 16
3.3 新型線性循環式二進制脈波偵測器電路 .................. 20
3.4 開迴路架構設計 .................. 27
3.5 全數位高速寬頻域線性循環二進制偵測脈波寬度鎖定迴路架構設計 ....... 34
3.6 全數位高解析工作週期矯正電路 .................. 44

四、全數位高速寬頻域二進制偵測脈波寬度鎖定迴路之電路設計 .................. 54
4.1 第一次偵測半週期碼控制訊號 .................. 54
4.2 停止訊號設計與重新偵測機制 .................. 55
4.3 週期碼與脈寬碼產生器子電路設計 .................. 58
4.4 比較器設計 .................. 61
4.5 脈寬碼矯正機制 .................. 64
4.6 脈波產生機制子電路 .................. 67
4.7 D型正反器電路 .................. 70

五、全數位高速寬頻域二進制偵測脈波寬度鎖定迴路模擬量測結果與硬體實現 ...... 71
5.1 模擬分析結果(Pre Sim) .................. 71
5.2 硬體實現 .................. 81
5.3 Post Sim 模擬結果 .................. 88

六、結論與未來改良方向 .................. 90
參考文獻 .................. 91
簡歷 .................. 94
[1] K. H. Cheng, et al. “A phase-locked pulsewidth control loop with programmable duty cycle.” in Proc. IEEE AP-ASIC2004, Aug 2004, pp.84-87.

[2] S. R. Han and S. I. Liu, “A 500-MHz-1.25-GHz fast-locking Pulse Width Control Loop with presettable duty cycle,” IEEE J. Solid-State Circuits, vol.39, no. 3, pp. 463 – 468, Mar. 2004.

[3] G. Jovanoviu‥, D. Mitiu‥, and M. Stojev “An Adaptive Pulse-Width Control Loop.” in Proc. IEEE Microelectronics, May 2006, pp.626-629.

[4] Navidi, M. M. and A. Abrishamifar. ”A fast lock time pulsewidth control loop using second order passive loop filters.” in Proc. IEEE ICEE, May 2011, pp.1-5.

[5] Yi-Ming Wang, and Jinn-Shyan Wang, “An all-digital Pulsewidth control loop,” in Proc. IEEE ISCAS, May. 2005, pp.23-26.

[6] Y. M. Wang, and J. S. Wang, e“An all-digital 50% duty-cycle corrector,” in Proc. IEEE on ISCAS ’04, May 2004,vol. 2, pp. II925-8.

[7] J. Gu, et al., ”ALL-Digital wide range precharge logic 50% duty cycle correc- tor.” IEEE Trans. VLSI Syst., vol. 20, no.4, pp.760-764, Apr. 2012.

[8] R. Swathi, M. B. Srinivas, ”All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex.” in Proc. IEEE Computer Society Annual Symposium on VLSI, May 2009, pp.258-262.

[9] R. M. Weng, Y. C. Lu, C. Y. Liu “A low jitter arbitrary-input pulsewidth control loop with wide duty cycle adjustment.” in Proc. IEEE ISCAS, May 2009, pp.1301-1304.

[10] 蕭明釗, ”循環取樣式脈波偵測技術之全數位脈波寬度鎖定迴路,” 國立雲林科技大學電子工程研究所碩士論文,民國九十八年六月。

[11] Levine, P.M.; Roberts, G.W, “A calibration technique for a high-resolution flash time-to-digital converter,” in Proc. IEEE International Symposium on Circuits and Systems, vol. 1, pp.253-256, May. 2004.

[12] Fenghao Mu and Christer Svensson, “Pulsewidth control loop in high-speed CMOS clock buffers,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 134-141, Feb. 2000.

[13] 汪威, 中華民國九十四年六月 ” Portable all-digital phase-lock loop circuit design with programmable pulse width control,” 國立台灣大學電子工程學研 究所碩士論文.

[14] 胡長芬, 中華民國九十年六月 ” An all-digital pulsewidth locked loop,” 國立中
正大學電機工程-研究所碩士論文.

[15] Shoa-Ku Kao, Bo-Jiun Chen and Shen-Iuan Liu, “A fast-locked all-digital delay- locked loop with non-50% input duty cycle,” in Proc. IEEE Electron Devices and Solid-State Circuits, Dec. 2007, pp. 1125-1128.

[16] ]Y. J. Wang, et al., “An all-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp.1262-1274, Jun. 2006.

[17] Madhumati, G. L. et al., “Comparison of 5-bit thermometer-to-binary decoders in 1.8V, 0.18um CMOS technology for flash ADCs,” in Proc. IEEE ICSPS, May2009, pp. 516-520.

[18] Bui Van, et al., “Thermometer-to-binary encoder with bubble error correction (BEC) circuit for flash analog-to-digital converter (FADC),” in Proc. IEEE ICCE, Aug. 2010, pp. 102-106.

[19] Bui Van, et al., “A new approach to thermometer-to-binary encoder of flash
ADCs-bubble error detection circuit,” in Proc. IEEE MWSCAS, Aug. 2011, pp. 1-4.

[20] 劉偉行、鄒昌廷、王晟瑋,“一種改良式可擴充之 8 位元數位比較器設計”,2008 Electronic Technolgy Symposium, , Jun. 2008.

[21] M. J. Kim and L. S. Kim , ”A 100MHz-to-1GHz fast-lock synchronous clock generator with DCC for mobile applications,” IEEE Trans. on Circ. and Syst- II., vol. 58, no. 8, Aug. 2011.

[22] J. W. Ke , S. Y. Huang and D. M. Kwai , ”A high-resolution all-digital duty- cycle corrector with a new pulse-width detector ,” in Proc. of Electron Devices and Solid-State Circuits, 2010.

[23] Kao, S. K. and S. I. Liu, “All-digital fast-locked synchronous duty-cycle cor- rector,” in Proc. IEEE Circuits and Systems II: Express Briefs, vol. 53, no. 12, pp. 1363-1367, Dec. 2006.

[24] Young-Jae, et al., “A 0.31-1 GHz fast-corrected duty-cycle corrector with suc- cessive approximation register for DDR DRAM applications,” IEEE Trans. VLSI Syst., vol. 20, no. 8, pp. 1-5, Aug. 2012.

[25] 蔡 承 熹, 中 華 民 國 九 十 八 年 六 月 ” An all digital pulsewidth locked using recyclable sampling detection technique,” 國立雲林科技大學電子工程研究所 碩士論文.

[26] 梁嘉碩, 中華民國九十四年六月 ” 可調脈寬之高速數位脈波寬度鎖定迴路” An adjustable pulsewidth of high speed digital pulsewidth locked loop,” 國立 雲林科技大學電子工程研究所碩士論文.

[27] Bo-Jiun Chen ,Shoa-Ku Kao and Shen-Iuan Liu, “An all-digital duty-cycle corrector,” in Proc. IEEE VLSI, Apr. 2006, pp. 1-4.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top