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研究生:林宥樺
研究生(外文):Yu-Hwa Lin
論文名稱:以提升優化指數為標的設計超寬頻低雜訊放大器
論文名稱(外文):Design of Ultra-Wideband CMOS LNA Based on Current-Reused Topology and Forward Body-Bias for High Figure of Merit
指導教授:許孟庭
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與光電工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:118
中文關鍵詞:低雜訊放大器電流再使用超寬頻順向基體偏壓技術
外文關鍵詞:ow noise amplifier (LNA)forward body-biasUWBLow power.current-reused
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本論文研製之低雜訊放大器(Low Noise Amplifier , LNA)電路利用台灣積體電路製造公司(TSMC)之0.18-μm CMOS製程技術實作完成,並於國家晶片中心(CIC)進行實際量測驗證效能。

本論文下線晶片是針對無線通訊系統前端的低雜訊放大器(Low noise amplifier),設計其工作頻帶在3.1GHz-12GHz(UWB)及3.1-10.6GHz之兩個LNA。

第一顆UWB LNA,採用LC網路作為輸入匹配,第二級使用電流再利用技術及基體偏壓技術,電流再利用主要為了提供較高的增益、增加隔絕度以及穩定度與消去共源極放大器的米勒效應,使高頻增益級足以提供在較高頻帶的增益;而基體偏壓技術,在相同的增益下,可降低功率消耗,量測結果,頻段為3.1 - 10.6GHz,電路最大增益達14.8 dB,輸入反射損耗小於-11.5與輸出小於-10.7dB,最低雜訊指數3.5dB,IIP3為-13dBm,供應電壓為1.1V,整體功率消耗為7.8mW。

第二顆UWB LNA,使用LC網路與源極退化電感作為輸入匹配,源極退化電感可提供良好的寬頻輸入匹配。第二級使用電流再利用技術,目的為提高增益、增加隔離度以及提升穩定度。量測結果,頻段為3.1 - 12GHz,電路最大增益為12.4dB,輸入反射損耗全頻段小於-15dB,輸出反射損耗小於-13.7dB,最低雜訊為3.41dB,IIP3為-12.8dBm,供應電壓為1.1V,整體功率消耗為11.2mW。
This thesis presents the research and implement on low noise amplifier for wireless communication system. The chip was fabricated by TSMC commercial 0.18-μm 1P6M CMOS technology. The efficiency of the circuit was demonstrated by measurement at National Chip Implementation Center (CIC).

The first chip, as using an LC matching network for the input matching. The second stage using Current-Reused Technique and Body-Bias to provide high gain, to increase isolation and stability and also eliminate the Miller effect of the common source amplifier, the high frequency gain stage effectively provide gain. Body bias can reduce power consumption with the same voltage gain. The maximum gain is 14.8 dB, input return loss is less than 11.5dB and the output is less than -10.7dB and minimum noise figure is about 3.5dB, the overall circuit power consumption is 7.8mW.

The second chip, as using an LC matching network and inductive source degeneration for input matching. The second stage using Current-Reused Technique to provide high gain increase isolation and stability. The maximum gain is 12.4dB, input return loss is less than -15dB, and the output return loss is less than -13.7dB, minimum noise figure is about 3.41dB, the overall circuit power consumption is 11.2mW.
中文摘要 ---------------------------------------------- i
英文摘要 ---------------------------------------------- ii
誌謝 ---------------------------------------------- iii
目錄 ---------------------------------------------- iv
表目錄 ---------------------------------------------- vi
圖目錄 ---------------------------------------------- vii

一、 緒論------------------------------------------ 1
1-1 研究背景-------------------------------------- 1
1-2 研究動機-------------------------------------- 2
1-3 論文組織-------------------------------------- 2
二、 低雜訊放大器---------------------------------- 3
2-1 UWB發展背景概述----------------------------- 3
2-2 阻抗匹配--------------------------------------- 5
2-2-1 阻抗匹配電路類型---------------------------6
2-3 品質因素探討----------------------------------- 8
2-3-1 分佈式放大器電路架構----------------9
2-3-2 LC網路加上源極退化電感----------------------10
2-3-3 並聯回授架構------------------------------ 11
2-3-4 共閘極寬頻架構-----------------------------13
2-3-5 各個架構之FOM比較--------------------------14
2-4 低雜訊放大器概述------------------------------- 15
2-5 雜訊------------------------------------------- 16
2-5-1 熱雜訊---------------------------------------- 17
2-5-2 散彈雜訊-------------------------------------- 18
2-5-3 閃爍雜訊---------------------------------18
2-5-4 電晶體雜訊--------------------------------20
2-5-4-1 通道熱雜訊------------------------21
2-5-4-2 感應閘極雜訊---------------------- 21
2-5-4-3 顫抖雜訊--------------------------22
2-6 散射參數--------------------------------------- 23
2-7 TSMC0.18μm 1P6M CMOS製程元件介紹------------ 24
2-7-1 MIM電容----------------------------------24
2-7-2 電阻-------------------------------------25
2-7-3 電感-------------------------------------25
2-7-4 CMOS電晶體高頻寄生電容----------------------26
三、 高增益超寬頻低雜訊放大器採用電流再利用與基體偏壓技術 27
3-1 電路架構簡介----------------------------------- 27
3-1-1 輸入匹配網路------------------------------ 28
3-1-2 電流再利用技術-----------------------------31
3-1-3 基體偏壓技術------------------------------34
3-1-4 輸出緩衝級--------------------------------37
3-2 FOM比較---------------------------------------- 39
3-3 電路設計與考量--------------------------------- 41
3-4 設計流程--------------------------------------- 42
3-5 電路佈局考量與模擬結果------------------------- 44
3-5-1 電路佈局考量------------------------------ 44
3-5-2 模擬結果----------------------------------45
3-6 量測結果--------------------------------------- 51
3-6-1 S參數特性---------------------------------52
3-6-2 雜訊指數特性-------------------------------54
3-6-3 非線性度特性-------------------------------55
3-7 結論------------------------------------------- 55
四、 使用電流再利用架構設計3-12GHz超寬頻低雜訊放大器 --------57
4-1 電電路架構簡介-------------------------------------57
4-1-1 輸入匹配網路------------------------------ 58
4-1-2 電流再利用架構-----------------------------60
4-1-3 輸出緩衝級---------------------------------60
4-2 FOM比較--------------------------------------- 66
4-3 電路設計與考量--------------------------------- 66
4-4 設計流程--------------------------------------- 68
4-5 電路佈局與模擬--------------------------------- 70
4-5-1 模擬結果----------------------------------71
4-6 量測結果--------------------------------------- 78
4-6-1 S參數特性---------------------------------79
4-6-2 雜訊指數和非線性特性-------------------------81
4-7 結論------------------------------------------- 84
五、 結果與討論------------------------------------- 85
5-1 高增益的超寬頻低雜訊放大器採用電流再利用與順向基底偏壓技術--85
5-2 使用電流再利用架構設計3-12GHz超寬頻低雜訊放大器---------87
六、 未來展望--------------------------------------- 90
參考文獻 ----------------------------------------------- 92
口試委員提問 ----------------------------------------96
簡介 ----------------------------------------------- 109
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