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研究生:洪仲
研究生(外文):Chung Hung
論文名稱:1~4G三軸加速度計與感測電路整合晶片
論文名稱(外文):1~4G integrated chip of three-axis accelerometer and sensing circuit
指導教授:薛雅馨薛雅馨引用關係
指導教授(外文):Ya-Hsin Hsueh
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與光電工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:63
中文關鍵詞:CMOS MEMS讀取電路三軸加速度計
外文關鍵詞:CMOS MEMStri-axis accelerometerreadout circu
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本論文是運用物理上的牛頓運動定律、虎克定律和電容基本原理等為基礎來設計加速度計的感測結構,並用靈敏度來衡量感測能力,為了便於製程上與電路整合,所以選擇電容式的感測方式。經過感測結構上細部之多次修改與模擬,使得在容許的面積考量下得到良好的感測能力,並且增加結構上的強度,使其能承受製程過程中的蝕刻應力。後端讀取電路架構,使用一般放大器為基本元件組成電容電壓轉換器,再搭配減法器組成電容感測讀取電路來處理感測訊號。最後將感測結構與讀取電路整合在一晶片裡,其目的為能實現一個可應用在居家照護偵測病患活動情形的電容式三軸加速度計與讀取電路整合晶片。使用Virtuoso和Laker軟體來進行設計,感測結構部分是使用CoventorWare模擬結構運動情形,電路部分是使用HSPICE進行波形的模擬驗證,所以模擬出三軸靈敏度為X:34.8mV/g、Y:20mV/g、Z:13.7mV/g,最後以TSMC 0.18μm CMOS MEMS製程來進行晶片下線製作。
This study applied Newton''s laws , Hooke''s law and the basic principles of capacitor as basis to design an accelerometer sensing structure, and use sensitivity to measure the sensing capability. For the convenience of circuit integration process , capacitive sensing method was adopted. After the sensing structure underwent several modification and simulation , the circuit showed good sensing capacity under limited area. The modification also increased the strength of the structure , which allowed it to endure etching stress during the process. The readout circuit architecture , used common amplifier as one of the basic components to implement a capacitor voltage converter , which was accompanied by a subtractor to form a capacitive sensing circuit to process sensing signal.
Finally, the sensing structure and readout circuit were integrated on a chip , to implement a capacitive tri-axis accelerometer and readout circuit integrated chip for homecare and for detecting patients’ activity. Virtuoso and Laker software were applied in design , and the structural movement of the sensing structure was simulated by CoventorWare. As for the circuit , HSPICE was applied for waveform simulation and verification. So simulate to three-axis sensitivity of X:34.8mV/g、Y:20mV/g、Z:13.7mV/g , and TSMC 0.18μm CMOS MEMS process was applied for the final tapeout.
目 錄

摘要 --------------------------------------------------------------- i
ABSTRACT ------------------------------------------------------- ii
目錄 --------------------------------------------------------------- iv
表目錄 --------------------------------------------------------------- vi
圖目錄 --------------------------------------------------------------- vii
一、 緒論------------------------------------------------------------ 1
1.1 研究背景------------------------------------------------- 1
1.2 研究動機------------------------------------------------- 2
1.3 文獻回顧------------------------------------------------- 2
1.4 論文架構--------------------------------------------------------- 4
二、 電容式加速度計結構設計與探討----------------------------------------- 5
2.1 電容式加速度計感測流程---------------------------------------------- 5
2.2 電容式加速度計物理運動原理------------------------------------------ 5
2.2.1 牛頓運動定律------------------------------------------------------ 5
2.2.2 電容基本原理------------------------------------------------------ 6
2.2.3 靈敏度----------------------------------------------------------- 7
2.3 電容式感測結構設計------------------------------------------------- 7
2.3.1 質量塊設計------------------------------------------------------- 8
2.3.2 感測臂設計------------------------------------------------------- 9
2.3.3 彈簧設計--------------------------------------------------------- 10
2.3.4 殘餘應力--------------------------------------------------------- 12
2.4 XY軸電容式加速度計結構--------------------------------------------- 14
2.4.1 XY軸不同加速度方向的位移模擬---------------------------------------- 15
2.4.2 XY軸給1~4G加速度各方向的位移模擬------------------------------------ 19
2.5 Z軸電容式加速度計結構---------------------------------------------- 20
2.5.1 Z軸不同加速度方向的位移模擬----------------------------------------- 21
2.5.2 Z軸在1~4G加速度下各方向的位移模擬----------------------------------- 24
2.6 三軸電容式加速度計之各軸數據---------------------------------------- 25
三、 電容感測讀取電路設計----------------------------------------------- 26
3.1 電容式感測架構---------------------------------------------------- 26
3.2 擬差動感測形式---------------------------------------------------- 26
3.3 電容式感測電路設計------------------------------------------------- 27
3.3.1 二級twostage OPA電路設計------------------------------------------ 27
3.3.2 電容電壓轉換電路-------------------------------------------------- 28
3.3.3 電容感測讀取電路設計----------------------------------------------- 30
3.4 電路模擬驗證------------------------------------------------------ 31
3.4.1 twostage OPA電路模擬--------------------------------------------- 31
3.4.2 電容感測讀取電路模擬----------------------------------------------- 33
3.5 三軸加速度計與讀取電路整合佈局與規格---------------------------------- 37
四、 三軸加速度計感測結構整合-------------------------------------------- 38
4.1 XYZ三軸整合感測結構----------------------------------------------- 38
4.2 XYZ軸不同加速度方向的位移模擬--------------------------------------- 42
4.3 XYZ軸給1~4G加速度各方向的位移模擬----------------------------------- 45
4.4 XYZ軸電容感測讀取電路模擬------------------------------------------ 46
4.5 三軸整合感測架構加速度計與讀取電路整合佈局與規格------------------------ 50
4.6 三軸加速度感測晶片比較--------------------------------------------- 51
五、 結論與未來展望---------------------------------------------------- 52
參考文獻 --------------------------------------------------------------- 53
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