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研究生:張仲凱
研究生(外文):Cheng-kai Chang
論文名稱:基於改良式反及閘全加器操作於次臨界區之超低功耗陣列乘法器
論文名稱(外文):Ultra Low Power Array Multiplier Based on Modified NAND Full Adder Scheme in Sub-threshold Region
指導教授:許明華許明華引用關係
指導教授(外文):Ming-hwa Sheu
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與光電工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:96
中文關鍵詞:加法器次臨界電壓製程偏移範圍乘法器反及閘
外文關鍵詞:Process cornerSub-threshold VoltageNAND gateAdder、Multiplier
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近年來,隨著VLSI製程技術不斷地進步,可攜帶型電子產品不斷地被改良與翻新,如醫療/生醫電子裝置、無線感測元件、智慧型手機等,這些產品主要需求低電壓以及低功率的消耗,因此如何降低操作電壓和功率消耗是為工程上的主要研究考量,由功率消耗的公式得知,操作電壓的下降能有效的達到降低功率消耗的目的,其主要操作環境是讓電路工作於次臨界區之內,因為考慮到操作電壓在低於電晶體臨界電壓下的環境工作,pMOS的特性將會變的較差,固然串聯也會對整體電路造成影響,所以我們選擇了pMOS無串聯的架構來組成加法器,其加法器的電路皆是由NAND閘來實現,接著應用所提出的加法器電路來組成一個陣列式乘法器。
我們採用TSMC-1P6M CMOS 0.18μm製程技術來做佈局後數據模擬(Post-Layout Simulation)以及下線製程。經由模擬可發現我們所提出來的架構可以達到170mV的低操作電壓,與傳統28T加法器以及TG加法器的操作電壓比來的更低,對於操作電壓的下降百分比分別為39%和11%,並且我們所提出的架構對於製程變異的影響更為小,最後我們將以實際晶片來進行佐證。從晶片實際量測我們的電路能夠達到100mV頻率為1KHz的環境下工作
In recent years, with the rapid evolution of VLSI process technology, many portable electronic products such as medical / biomedical electronic devices, wireless sensing element and smart-phones etc are constantly being designed and implemented. These products are required low voltage and low power consumption. How to reduce the operating voltage and power dissipation becomes the main design consideration in engineering. Based on the formula of the power consumption, the supply voltage can be decreased to reduce power dissipation effectively. For this reason, the circuit design for ultra low voltage could operate in the sub-threshold region. Under the threshold voltage, pMOS characteristics will become degradation. Therefore the pMOS series affect the performers of whole circuit. So the full adder is composed by using NAND gate such that all pMOS are designed in parallel. Afterward we use the adder to make up a 8x8 array multiplier.
Our ultra low-voltage multiplier is implemented and fabricated based on TSMC-1P6M 0.18μm CMOS process to verify the circuit performance. From the simulation results, the minimum operating voltage of our design is at 170mV. Its supply voltage has 39% and 11% lower than those of traditional 28T and TGA designs respectively. In addition, the process variation is also considered in our design. Finally, the chip measurement can reach to 100mV with 1KHz working frequency.
中文摘要 i
ABSTRACT ii
目 錄 iii
表目錄 v
圖目錄 vi
第一章 緒論 1
1-1 研究動機與背景 1
1-2 內容大綱 1
1-3 功率消耗介紹 1
1-3-1 功率消耗分析 2
1-3-2 資料切換機率分析 2
1-3-3 靜態功率消耗 4
1-4 次臨界區介紹 5
第二章 加法器/乘法器介紹及分析與相關研究 8
2-1 前言 8
2-2 加法器架構介紹 8
2-2-1 靜態CMOS邏輯 9
2-2-2 通過式邏輯 10
2-2-3 Design[12]加法器 12
2-3 乘法器架構介紹 12
2-4 次臨界區加法器介紹 13
2-4-1 Tiny-XNOR 14
2-4-2 TG-XNOR 15
2-4-3靜態CMOS架構XNOR 15
2-4-4混合式邏輯閘XNOR 16
第三章 使用改良式反及閘全加器設計之陣列乘法器組成 17
3-1 電路分析 17
3-2 所提出之改良式反及閘全加器介紹 21
3-2-1反及閘加法器介紹 21
3-2-2改良式反及閘加法器 24
第四章 模擬結果與晶片實現驗證 27
4-1 設計流程與模擬環境介紹 27
4-1-1 晶片設計流程 27
圖4-1 設計方塊流程圖 27
4-1-2 模擬環境介紹 28
4-2 模擬結果 28
4-3 晶片實現 31
4-3-1 晶片量測規劃 31
4-3-2 內部電路架構 32
4-4 晶片量測 34
4-4-1 改良式反及閘加法器之乘法器晶片實現 34
4-4-2 量測環境 36
第五章 結論 38
參考文獻 39
口試Q&;A 42
附錄. 49
[1]J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, A Design perspective, ser. Electron and VLSL, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 2003.

[2]G. Schrom, S. Selberherr,“Ultra low power CMOS technologies, ”Int. Semiconductor conf., vol. 1, pp. 237-246, Oct. 1996.

[3]S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid-Pecht, A. Fish, “Digital subthreshold logic design-motivation and challenges, ” IEEE Electrical and Electronics Engineers in Israel, pp. 702-706, Dec. 2008.

[4]B. Nikolic, V. G. Oklobzija, V. Stojanovic, W. Jia, J.K. Chiu and M.M. Leung, “Improved Sense-Amplifier-Based Flip Flop: Design and Measurement,”IEEE J. Solid-State Circuits, vol. 35, pp.876-883, June. 2000.

[5]Jin-Fa Lin , Yin-Tsung Hwang, Ming-Hwa Sheu and Cheng-Che Ho,“A High Speed and Energy Efficient Full Adder Design Using Complementary &; Level Restoring Carry Logic,”IEEE International Symposium on Circuit and System, pp. 2705-2708, May. 2006.

[6]R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus Pass-transistor logic,” IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079–1090, July.1997.

[7]K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A.Shimizu, “A 3.8-ns CMOS 16_16-b multiplier using complementary pass-transistor logic,” IEEE J. Solid-State Circuits, vol. 25, pp. 388–395, Apr. 1990.

[8]N. Zhuang and H. Wu, “A new design of the CMOS full adder,” IEEE J. of Solid state circuits, vol. 27, pp. 840-844, May. 1992.

[9]A. Shams, T. Darwish, and M. Bayoumi, “Performance analysis of low power 1-bit CMOS full adder cells,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 10, no. 1, pp. 20–29, Feb. 2002.

[10]D. Radhakrishnan, “Low-voltage low-power CMOS full adder,” Proc. IEE Circuits,Devices and Systems, vol. 148, no. 1, pp. 19–24, Feb. 2001.

[11]Chip-Hong Chang; Jiangmin Gu and Mingyan Zhang, “A review of 0.18um full adder performances for tree structured arithmetic circuits,” IEEE Trans. Very Large Scale Integr. (VLSI) System, vol. 13, no. 6, pp. 686 – 695, June. 2005.

[12]S. Goel, A. Kumar, M.A. Bayoumi, “Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style,” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 14, no.12, pp. 1309-1321, Dec. 2006.

[13]H. Soeleman, K. Roy, “Ultra-low power digital subthreshold logic circuits, ” Low Power Electronics and Design, pp. 94-96, Aug. 1999.

[14]A. Wang, A Chandrakasan, “A 180-mV subthreshold FFT processor using a minimum energy design methodology, ” IEEE J. of Solid state circuits, vol. 40, no. 1, pp. 310–319, Jan. 2005.

[15]B.H. Calhoun, A Wang, A Chandrakasan, “Modeling and sizing for minimum energy operation in subthreshold circuits, ” IEEE J. of Solid state circuits, vol. 40, no. 9, pp. 1778–1786, Sept. 2005.

[16]V. Moalemi, A. Afzali-Kusha, “Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies,” IEEE Computer Society Annual Symposium on VLSI. pp. 514–515, Mar. 2007.


[17]A. Bellaouar and M. I. Elmasry, “Low-Power Digital VLSI Design Circuit and System,”Reading, MA: Kluwer Academic Publisher, 1995.

[18]王進賢, “VLSI 電路設計,” 高立圖書有限公司, 中華民國89年9月

[19]L. Ding and P. Mazumder, “Dynamic noise margin: Definitions and model,” in Proc. 17th Int. Conf. VLSI Design, pp. 1001–1006, 2004.
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