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研究生:李榮辰
研究生(外文):Rong-chen Li
論文名稱:快速影像標籤化與物件特徵擷取之VLSI設計
論文名稱(外文):VLSI Design of Single Pass Labeling and Feature Extraction for Image Object Detection
指導教授:許明華許明華引用關係
指導教授(外文):Ming-Hwa Sheu
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與光電工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:135
中文關鍵詞:標籤化特徵擷取物件偵測單一次掃描快速掃描
外文關鍵詞:Feature ExtractionFast ScanningObject DetectionSingle-PassLabeling
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影像前景物件連接特性分析一直是電腦機器視覺影像處理重要的一環,在許多影像處理的前置作業中,影像前景物件切割的結果往往不是那麼理想,某些前景物件會有些許的呈現破碎情形,並且都分佈在同一區域。由於前景物件切割的正確率嚴重影響到後續影像處理的結果,所以使用標籤化前景物件來判斷這些破碎的前景物件是否相連接,藉由快速掃描原圖影像來記錄這些破碎物件的特徵資訊,並且偵測出被切掉的前景物件相關資訊,或者偵測出前景物件所在的座標位置、邊界線、中心點、所占面積資訊等等,甚至是更進一步濾除不必要的雜訊,這些效果都對後續的影像處理有著很重要關連。
  本篇論文研究主要貢獻在於提出可快速掃描且具備三個標籤合併表以及一個特徵資料蒐集表的快速標籤化演算法,利用標籤回收再使用的方式搭配三個標籤合併表來減少記憶體的使用量,再藉由簡單的幾個判斷步驟來決策掃描中的像素其標籤值以減短執行時間。從實驗結果顯示,我們提出的演算法可以減少平均12.8%的執行時間,影像複雜度越高越顯卓,以及減少平均38%的記憶體使用量。
  另外,將本論文提出之演算法架構實現硬體,使用平行架構搭配快速標籤合併演算法,以及標籤合併表的切換來減低系統執行時間,可以提升平均23%的電路工作頻率,以及節省平均約20%的FPGA資源使用量。
Connected components analysis is a very important step to a computer machine vision. In image processing, the foreground object segmented results are often less than ideal such that the segmentation will have a little broken. Since the correct rate of the foreground object segmentation seriously affects the feature extraction and subsequent image processing, many approaches use single pass labeling technique to detect all connected components of broken foreground objects. At the same time, the feature information of foreground objects can be obtained in labeling. These functions are required for real-time operation.
The main contribution of this paper is to propose a fast single pass labeling algorithm that only has three label merging tables and a feature data collection table. The label reused methods is combined with three labels tables to reduce memory usage, through a few simple steps to check neighbors and determine current pixel. The experimental results show that our proposed algorithm can reduce the average CPU execution time of 12.8%. For the higher complexity of the image input, our method can reduce average of 38 % memory usage. In addition, this paper design a VLSI architecture based on our proposed algorithm. This architecture has been implemented on FPGA which can improve the average 23 % of operating frequency, and save about 20% FPGA logic gates usage.
中文摘要
ABSTRACT
目錄
表目錄
一、 緒論與相關文獻
1.1 研究動機與目的
1.2 相關文獻探討
二、 Single Pass Labelling演算法效能分析
2.1 標籤決策以及標籤合併控制
2.1.1 RT、DT、FT
2.1.2 標籤的決策
2.2 演算法驗證結果與分析
2.2.1 實例模擬
2.2.2 軟體模擬
三、 Single Pass Labelling VLSI設計與FPGA實現數據分析
3.1 硬體架構
3.2 FPGA數據結果分析
3.2.1 Quartus 12.1 波形模擬
3.2.2 FPGA 合成
3.2.3 FPGA 驗證
3.3 Design Compiler Synthesis
四、 總結
4.1 結論
4.2 未來展望
[1] R.M. Haralick, “Some neighborhood operations,” in real time/parallel computing image analysis, Plenum Press, New York, pp.11-35, 1981.

[2] H. Flatt, S. Blume, S. Hesselbarth, T. Schuemann, and P. Pirsch, “A Parallel Hardware Architecture for Connected Component Labeling based on Fast Label Merging,” Int’l Conf. App.-Spec. Arch. and Processors, pp. 144-149, July 2008.

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[4] H. Hedberg, F. Kristensen, and V. Owall, “Implementation of a labeling algorithm based on contour tracing with feature extraction,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1101.-1104, May 2007.

[5] C.T. Johnston and D.G. Bailey, “FPGA implementation of a Single Pass Connected Components Algorithm”, in IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2008), Hong Kong, pp. 228-231, Jan. 2008.

[6] Thornberg et al. “Real-time Component Labelling and Feature Extraction on FPGA,” Int’l symp on Signals, Circuits and Systems, ISSCS, pp. 1-4, 2009.

[7] Holger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Sch‥unemann, and Peter Pirsch” A Parallel Hardware Architecture for Connected Component Labeling Based on Fast Label Merging” Appelstr. 4, IEEE Application-Specific Systems, Architectures and Processors, pp. 144-149, 2008

[8] A. Rosenfeld and J. Pfaltz, "Sequential operations in digital picture processing", Journal of the ACM, 13(4), pp. 471-494, 1966

[9] M. Jablonski and M. Gorgon, “Handel-C implementation of classical
component labelling algorithm,” in Digital System Design, DSD. Euromicro Symposium on, pp. 387–393. 2004

[10] D. Bailey and C. Johnston, “Single pass connected components
analysis,” in Image and Vision Computing New Zealand, pp. 282–287. 2008

[11] C. Johnston and D. Bailey, “FPGA implementation of a single pass connected components algorithm,” Electronic Design, Test and Applications, pp. 228–231, 2008.

[12] Ni Ma, Donald G. Bailey, Christopher T. Johnston “Optimised Single Pass Connected Components Analysis” , IEEE , Digital Object Identifier , pp. 185-192, 2008

[13] Mayssaa A. Najjar, Swetha Karlapudi, and Magdy A. Bayoumi, Fellow, “Memory-Efficient Architecture for Hysteresis Thresholding and Object Feature Extraction” , IEEE, Transactions Image Processing, Vol. 20, No. 12, 2011
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