臺灣博碩士論文加值系統

在未來無線通訊傳輸系統下，為了增加傳輸的品質，無線通訊系統都開始採用先進的通道碼 (Channel Coding) 技術，其中以渦輪碼(Turbo Code)與低密度奇偶校驗碼(Low-Density Parity-Check, LDPC)，此兩種錯誤更正碼具有非常優異的解碼能力，為現今較常使用之錯誤更正碼。
現今設計一個最佳前向錯誤更正裝置，需要考慮高彈性與不同通訊標準協定。本論文中，提出多模式以四為基底的軟式輸入軟式輸出核心，利用前向和後向解碼演算法與進階最大事後機率解碼演算法，達到運算單元共用的目的。此外，所提出的多模式以四為基底的軟式輸入軟式輸出核心，可同時支援單二元與雙二元渦輪碼和低密度奇偶校驗碼解碼。最後本論文利用TSMC 90nm CMOS製程實現硬體，在操作頻率為167MHz，晶片核心面積大小為0.45mm2。在有效率的硬體成本下，多模式以四為基底的軟式輸入軟式輸架構相較於單一的單二元渦輪碼架構、單一雙二元渦輪碼架構與單一低密度奇偶校驗碼解碼架構結合下，可以達到大約48.43%面積減少。

In order to increase the quality of the transmission, the wireless communication systems adopt advanced channel coding technology , including Turbo Code and (Low-Density Parity-Check, LDPC) codes. These two error correction codes have a very excellent decoding capability in the present generation.
To design a batter forward error correction device that needs to consider high flexible and different communication standards, we propose an area-efficient radix-4 soft-input soft-output (SISO) kernel alternatively that employs the forward and backward algorithm and enhanced Max-log-maximum a posteriori algorithm by sharing computational units. Moreover, the proposed multi-mode radix-4 SISO kernel is to support single/double binary turbo codes (SBTC/DBTC) and low-density parity-check (LDPC) codes. Finally, the proposed SISO decoder is implemented and fabricated in TSMC 90nm CMOS technology. The core size is 0.45 mm2 with operating frequency of 167 MHz. The multi-mode radix-4 SISO kernel achieves 48.43% area reductions compared with integrated individual SBTC, individual DBTC, and individual (LDPC) decoding architectures.

摘要 i
Abstract ii
誌謝 iii
List of Contents iv
List of Tables vi
List of Figures vii
Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation and Goal 3
1.3 Thesis Organization 6
Chapter 2 Review of Turbo Codes 7
2.1 Turbo Encoder/Decoder Structure 7
2.2 Decoding Algorithm for SISO Decoder 9
2.2.1 MAP Algorithm 10
2.2.2 Radix-4 SB EML-MAP algorithm for turbo decoding 11 2.2.3 Radix-4 DB EML-MAP algorithm for turbo decoding 12
2.3 Timing Chart of MAP Decoding 13
2.3.1 Sliding Window Approach 13
2.3.2 Parallel Window Approach 14
Chapter 3 Review of Low-Density Parity-Check Codes 16
3.1 LDPC Encoder/Decoder Structure 16
3.2 Decoding Algorithm for SISO Decoder 20
3.2.1 Sum Product Algorithm 21
3.2.2 Forward Backward Algorithm 23
3.2.3 Radix-4 FBA for LDPC decoding 24
3.3 Timing diagram of FBA Decoding 27
Chapter 4 Proposed Multi-Mode Radix-4 SISO Kernal Design 29
4.1 Key Components Design for Multi-mode Radix-4 SISO Kernel 29
4.1.1 The Architecture of SISO kernel 29
4.1.2 The timing diagram for SISO kernel 30
4.1.3 Branch Metrics Uints 33
4.1.4 Recursion Processor Unit 35
4.1.5 A-posteriori Calculator Uint 40
4.1.6 Extrinsic Calculator Uint 44
Chapter 5 VLSI Implementation of Multi-Mode Radix-4 SISO Kernal Design 45
5.1 Determation of Worldlength 45
5.2 Hardware Overhead Analysis of Proposed SISO Kernel 47
5.3 Throughput Analysis 49
5.4 Chip Implementations 51
5.5 Comparisons 53
5.6 Application of the Protoyping Design 55
Chapter 6 Conclusion 61
References 62

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