臺灣博碩士論文加值系統

本論文講述應用於專用短距離通訊系統之低功耗高線性度之混頻器設計。此混頻器使用臺積電提供之0.18 um CMOS 1P6M 製程。本設計使用類似Gilbert-cell架構作雙平衡操作，為取得較佳的雜訊指數與線性度特性，將其設計成電阻性混頻方式，並將本地振盪訊號從基底／源極端輸入，利用基底注入技術降低混頻器的功耗以及本地振盪所需功率。
電路經量測，在降頻模式中，混頻器的轉換損耗為16.26 dB，輸入 1 dB 壓縮點 1.5 dBm，輸入三階截斷點為 13 dBm，雜訊指數與功耗分別為15.41 dB與0.16 mW；在昇頻模式中，混頻器的轉換損耗為18.53 dB，輸入/輸出 1 dB 壓縮點分別為-4.5 dBm以及-13 dBm，輸入與輸出三階截斷點點分別為-3 dBm以及-7 dBm。

This paper presents a low power consumption and high linearity mixer design for dedicated-short-range-communications (DSRC) applications. The designed mixer is in the double-balanced configuration similar to the Gilbert-cell structure, The mixer core is worked at the triode region to perform the resistive mixing for better noise figure and linearity, the local oscillator (LO) signal is applied to the bulk and the source terminals in order to use the bulk-injection method to reduce the required LO power and dc power consumption.
In the down-convert mode, the measured conversion loss and input 1-dB compression point are about 16.26 dB and 1.5 dBm, the input third-order intercept point (IP3) of 13 dBm, the noise figure and power consumption are about 15.41 dB and 0.16 mW; in the up-convert mode, the measured conversion loss is about 18.53 dB, the input and output 1-dB compression point are about -4.5 dBm and -13 dBm, the input and output IP3 are about -3 dBm and -7 dBm.

第一章 緒論‧‧‧‧‧‧‧‧‧‧‧‧‧1
1.1 研究背景‧‧‧‧‧‧‧‧‧‧‧‧‧1
1.2 研究動機‧‧‧‧‧‧‧‧‧‧‧‧‧3
1.3 章節簡述‧‧‧‧‧‧‧‧‧‧‧‧‧4
第二章 應用於DSRC系統之設頻傳收機‧‧‧‧‧‧‧‧‧‧‧‧‧5
2.1 DSRC系統之介紹‧‧‧‧‧‧‧‧‧‧‧‧‧5
2.2 射頻傳收機‧‧‧‧‧‧‧‧‧‧‧‧‧8
2.2.1 簡介‧‧‧‧‧‧‧‧‧‧‧‧‧8
2.2.2 射頻傳收機介紹‧‧‧‧‧‧‧‧‧‧‧‧‧8
2.2.3 直接轉換式傳收機‧‧‧‧‧‧‧‧‧‧‧‧‧8
2.2.4 超外差式傳收機‧‧‧‧‧‧‧‧‧‧‧‧‧12
2.2.5 低中頻傳收機‧‧‧‧‧‧‧‧‧‧‧‧‧14
2.3 射頻傳收機之重要參數‧‧‧‧‧‧‧‧‧‧‧‧‧15
2.3.1 靈敏度‧‧‧‧‧‧‧‧‧‧‧‧‧15
2.3.2 雜訊‧‧‧‧‧‧‧‧‧‧‧‧‧16
2.3.3 1 dB壓縮點與動態範圍‧‧‧‧‧‧‧‧‧‧‧‧‧17
2.3.4 互調失真‧‧‧‧‧‧‧‧‧‧‧‧‧19
第三章 混頻器基本原理 22
3.1 概述‧‧‧‧‧‧‧‧‧‧‧‧‧22
3.2 混頻器之重要性能參數‧‧‧‧‧‧‧‧‧‧‧‧‧24
3.2.1 轉換增益‧‧‧‧‧‧‧‧‧‧‧‧‧24
3.2.2 雜訊指數‧‧‧‧‧‧‧‧‧‧‧‧‧24
3.2.3 隔離度‧‧‧‧‧‧‧‧‧‧‧‧‧25
3.2.4 1 dB壓縮點‧‧‧‧‧‧‧‧‧‧‧‧‧26
3.2.5 三階截斷點‧‧‧‧‧‧‧‧‧‧‧‧‧26
3.3 主動式以及被動式混頻器‧‧‧‧‧‧‧‧‧‧‧‧‧28
3.3.1 被動式混頻器‧‧‧‧‧‧‧‧‧‧‧‧‧29
3.3.2 單端平衡式混頻器‧‧‧‧‧‧‧‧‧‧‧‧‧29
3.3.3 雙端平衡式混頻器‧‧‧‧‧‧‧‧‧‧‧‧‧32
第四章 應用於DSRC系統之混頻器‧‧‧‧‧‧‧‧‧‧‧‧‧36
4.1 系統考量‧‧‧‧‧‧‧‧‧‧‧‧‧36
4.2 電路設計架構‧‧‧‧‧‧‧‧‧‧‧‧‧38
4.3 模擬與量測結果‧‧‧‧‧‧‧‧‧‧‧‧‧40
4.3.1 模擬環境‧‧‧‧‧‧‧‧‧‧‧‧‧40
4.3.2 量測方法與校正考量‧‧‧‧‧‧‧‧‧‧‧‧‧41
4.3.2.1 校正考量‧‧‧‧‧‧‧‧‧‧‧‧‧41
4.3.2.2 量測方法‧‧‧‧‧‧‧‧‧‧‧‧‧43
4.3.3 模擬與量測結果‧‧‧‧‧‧‧‧‧‧‧‧‧45
第五章 結論‧‧‧‧‧‧‧‧‧‧‧‧‧59

參考文獻‧‧‧‧‧‧‧‧‧‧‧‧‧60

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