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研究生:徐永豪
研究生(外文):Yung-Hao Hsu
論文名稱:多核心記憶體架構下工作屬性驅動之適應性更新與緩衝機制
論文名稱(外文):Task Attribute Enabled Adaptive Refresh and Buffering for Multi-core Memory Architecture
指導教授:鄭維凱鄭維凱引用關係
指導教授(外文):Wei-Kai Cheng
學位類別:碩士
校院名稱:中原大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:55
中文關鍵詞:混合式記憶體多核心相位變動式記憶體
外文關鍵詞:hybrid memory systemPCRAMmulti-core
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近年來,混合式記憶體系統研究越來越受重視。其原理是藉由將不同的記憶體混合應用,並互取各個記憶體系統的優點,以達到最佳化目標的記憶體系統。
相位變動式記憶體(Phase Change Random Access Memory - PCM、PCRAM)相較於動態隨機存取記憶體(Dynamic Random Access Memory - DRAM)擁有較高的密度及較小的靜態消耗,但寫入延遲及寫入耗能較高,其使用壽命也較短。
本篇論文將PCRAM與DRAM整合並提出在DRAM的適應性更新及緩衝機制。將PCRAM作為主記憶體,而DRAM作為最末端快取記憶體配置。當有讀寫需求時,先到DRAM做讀寫請求以降低PCRAM寫入所造成的耗能及效能缺陷,並計算不同核心所使用的記憶體區塊大小,給予不同的刷新及緩衝配置。當資料超過配置時間沒被讀寫時,則停止刷新並將資料寫回PCRAM,以降低DRAM靜態耗能。
在這混和式記憶體架構與更新及緩衝機制下,藉由我們的實驗結果證明,跟傳統的DRAM相比較能取得耗能的優化,跟PCRAM相比較能取得良好的效能優化。


The research of Hybrid Memory System has been emphasized in recent years. Hybrid memory architecture takes the advantage of different memory technologies to reduce leakage power consumption. Compared with dynamic random access memory (DRAM), phase change random access memory (PCRAM) has higher cell density and lower leakage power. Nevertheless, it has higher write latency, write energy, and shorter write endurance.
In this paper, we propose a task attribute enabled adaptive refresh and buffering methodology for hybrid memory structure, in which we take PCRAM as main memory and DRAM as last level cache. Each task executing on the CPU has different refresh and buffer limits of DRAM banks utilization based on their task attribute. When CPU sends read/write requests to memory controller, DRAM will be used firstly to reduce write energy and write latency. Then, when the data is not accessed on DRAM after the refresh limit period, we stop its refresh operations and write back to PCRAM in order to reduce leakage power of DRAM.
Based on our task attribute enabled adaptive refresh and buffering technique, experimental results show that our hybrid memory structure method not only has a better static leakage power reduction compared with DRAM architecture, but also has a better access latency compared with the PCRAM architecture.


目錄

中文摘要 I
ABSTRACT II
致謝 III
目錄 IV
圖目錄 V
表目錄 VI
第一章 、前言 1
第二章 、問題描述與相關研究 4
2.1 研究動機 4
2.2 研究動機 8
2.3 相關研究與演算法簡介 9
2.3.1 混和式記憶體之相關研究 9
2.3.3 混和式記憶體功率消耗管理之相關研究 11
第三章 、演算法與程式流程 14
3.1 程式流程 14
3.2 使用架構 15
3.3 演算法 16
3.3.1 Task Generation 16
3.3.2 DRAM Simulation 19
3.3.3 PCRAM Simulation 21
3.3.4 Dynamic Refresh 25
第四章 、實驗結果 31
4.1 執行平台與程式語言 31
4.2 實驗結果 32
4.2.1 Task Type 32
4.2.2 Dynamic Refresh 34
第五章 、結論與未來發展 45
參考文獻 46
作者簡介 49

圖目錄
圖2-1:DRAM預設配置範例 7
圖2-2:The temperature-time relationship during SET and RESET operations 10
圖2-3:DRAM Cache Hybrid Memory System 12
圖2-4:限制時間與效能、耗能關係圖 13
圖2-5:動態限制時間控制 13

圖3-1:程式流程圖 14
圖3-2:混和式記憶體系統之整體架構 15
圖3-3:Gem5工具:工作執行指令的詳細資訊 17
圖3-4:Gem5工具:工作整體執行的詳細資訊 18
圖3-5:CACTI 6.5 – Configure File 19
圖3-6:CACTI 6.5 模擬DRAM記憶體模組之結果 20
圖3-7:NVsim – Configure File 22
圖3-8:NVsim – Cell File 23
圖3-9:NVsim 模擬PCRAM記憶體模組之結果 24
圖3-10:DRAM更新維護資料之時間週期調整及Replace或Buffer allocation執行流程 25
圖3-11:Bank request之Hit情況 26
圖3-12:Bank request之存在Empty Bank 27
圖3-13:Bank request之未達到配置限制並以Replace機制替換 27
圖3-14:Bank request之其本身有超過一半Base counter的Bank 28
圖3-15:Bank request之Buffer allocation機制 29
圖3-16:Bank request之Replace機制 29

圖4-1:Energy比較結果 43
圖4-2:Latency比較結果 44

表目錄
表2-1:根據工作特性及工作即時性需求之分類 5
表2-2:各種記憶體之特性比較 9

表3-1:範例預設配置記憶體區塊大小與維護更新資料週期之限制 25

表4-1:實驗環境及參數設定 31
表4-2:SPEC CPU2006讀寫比例及讀寫位置比例(250萬筆指令) 33
表4-3:SPEC CPU2006 Type分類 33
表4-4:Benchmark組成Type及組成內容 34
表4-5:Benchmark1實驗總結果 34
表4-6:Benchmark2實驗總結果 35
表4-7:Benchmark3實驗總結果 35
表4-8:Benchmark4實驗總結果 35
表4-9:Benchmark5實驗總結果 36
表4-10:Benchmark6實驗總結果 36
表4-11:Benchmark7實驗總結果 36
表4-12:Benchmark8實驗總結果 37
表4-13:Benchmark9實驗總結果 37
表4-14:Benchmark1 Read/Write Latency實驗結果 37
表4-15:Benchmark2 Read/Write Latency實驗結果 38
表4-16:Benchmark3 Read/Write Latency實驗結果 38
表4-17:Benchmark4 Read/Write Latency實驗結果 38
表4-18:Benchmark5 Read/Write Latency實驗結果 38
表4-19:Benchmark6 Read/Write Latency實驗結果 39
表4-20:Benchmark7 Read/Write Latency實驗結果 39
表4-21:Benchmark8 Read/Write Latency實驗結果 39
表4-22:Benchmark9 Read/Write Latency實驗結果 39
表4-23:Benchmark1 Read/Write Energy、Leakage、Refresh實驗結果 40
表4-24:Benchmark2 Read/Write Energy、Leakage、Refresh實驗結果 40
表4-25:Benchmark3 Read/Write Energy、Leakage、Refresh實驗結果 40
表4-26:Benchmark4 Read/Write Energy、Leakage、Refresh實驗結果 41
表4-27:Benchmark5 Read/Write Energy、Leakage、Refresh實驗結果 41
表4-28:Benchmark6 Read/Write Energy、Leakage、Refresh實驗結果 41
表4-29:Benchmark7 Read/Write Energy、Leakage、Refresh實驗結果 42
表4-30:Benchmark8 Read/Write Energy、Leakage、Refresh實驗結果 42
表4-31:Benchmark9 Read/Write Energy、Leakage、Refresh實驗結果 42

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