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研究生:王泓翔
研究生(外文):Hung-Hsiang Wang
論文名稱:積體電路之靜電放電元件改善與分析
論文名稱(外文):The Study of Silicon Integration Circuit of ESD Protection Devices Improvement and Analysis
指導教授:鄭湘原
指導教授(外文):Erik S- Jeng
學位類別:碩士
校院名稱:中原大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:53
中文關鍵詞:閘極與基底耦合觸發電路靜電放電保護元件GGNMOSSilicided靜電放電傳輸線路脈衝LDD
外文關鍵詞:Gate and Base Trigger circuitry protection deviceSilicideGGNMOSTransmission Line PulseElectrostaticLightly Dope Drain
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生活在一個講究多功能、省電及體積小的可攜式電子產品的時代,消費者對於可攜式電子產品的輕薄體積、多重性與待機時間的要求,對從事電子工程研究的人員是一項大挑戰。如何在一個小面積的電子電路元件上設計出多功能、省電及高可靠度能力(如高靜電放電保護能力)將會是值得深入研究的一門技術。
此論文將對高可靠靜電放電能力、靜電放電現象、產業界靜電放電測試方式(人體靜電放電測試模式、機械靜電放電測試、元件充電測試模式及傳輸線路脈衝),靜電放電造成破壞分析方式,深次微米靜電放電保護元件(二極體、雙極體、金屬氧化物半導體與矽控整流) 保護元件特性分析及Layout設計參數考量,製程技術上隨著CMOS 尺寸的縮小及製程加入LDD 與Silicided 作深入研究。
本研究實驗將透過台灣積體電路公司0.25um Mix-Mode 製程來進行深次微米靜電放電保護元件之GGNMOS 測試件設計及驗證,論文最後會介紹靜電放電保護元件無需增加光罩及製程的閘極與基底耦合觸發電路靜電放電保護元件及結論。


In a modern portable electronics, requirements of products, such as multiple functions, power efficient and appropriate size, need to be optimized. However, the current challenge for electrical and electronic engineering researcher is to design portable electronic devices with power efficiency and robust in anti-electrostatic discharges.
This study aims to investigate issues in the Electrostatic Discharge (ESD), which includes electrostatic phenomenon, electrostatic performance, industry electrostatic test methods (Human body mode, Machine mode, Charge device mode and Transmission line pulse measurement), Electrostatic charge devices (Diode, Field oxide device, Gate ground NMOS, and Silicon Controlled
Rectifier) and layout design parameters in submicron technology. In addition, we also analyzed the influence of adding LDD and Silicide on ESD protection in the same technology.
The experimental verification was accomplished by the sub-micron Gate ground NMOS ESD protection device which was fabricated by commercially
available foundry 0.25um mixed mode process technology. We also introduced the ESD device with maskless process and discussed the gate and base couple trigger circuitry protection device in the last portion of this thesis.


目錄
中文摘要..................................................................................................................................... I
Abstract ......................................................................................................................................II
致 謝................................................................................................................................ IV
目錄............................................................................................................................................V
圖目錄...................................................................................................................................... VI
表目錄.....................................................................................................................................VII
第一章導論.............................................................................................................................. 1
第一章 導論........................................................................................................................ 2
1-1 前言............................................................................................................................ 2
1-2 靜電放電現象............................................................................................................ 5
1-3 靜電放電對積體電路造成傷害............................................................................ 8
第二章靜電放電測試與量測................................................................................................ 13
第二章靜電放電測試與量測................................................................................................ 14
2-1 人體靜電放電測試模式.......................................................................................... 15
2-2 機械靜電放電測試模式.......................................................................................... 16
2-3 元件充電測試模式.................................................................................................. 16
2-4 靜電放電失效分析.................................................................................................. 17
第三章靜電放電元件............................................................................................................ 21
第三章靜電放電元件............................................................................................................ 22
3-1 二極體Diode...................................................................................................... 23
3-2 厚氧化層電晶體FOD........................................................................................ 24
3-3 金屬氧化物半導體MOS........................................................................................ 26
3-4 矽控整流SCR.................................................................................................... 27
第四章實驗測試件與分析.................................................................................................... 30
第四章 靜電放電測試件實驗與分析.............................................................................. 31
4-1 測試件元件設計....................................................................................................... 32
4-2 傳輸線路脈衝量測系統的組成............................................................................... 34
4-3 測試件元件量測結果.......................................................................................... 38
第五章結論與未來展望........................................................................................................ 40
5-1 結論...................................................................................................................... 41
5-2 未來展望.............................................................................................................. 41
Reference ................................................................................................................................. 43
個人簡介.................................................................................................................................. 46

圖目錄
Figure 1-1 Input/Output 放置靜電保護元件........................................................................... 3
Figure 1-2 製程技術的演進對於靜電放電能力的影響......................................................... 3
Figure 1-3 MOS 元件輕掺雜源極及汲極製程LDD 結構................................................ 4
Figure 1-4 MOS 元件金屬矽化製程Silicide結構................................................................. 5
Figure 1-5 IC常見的異常現象分部圖[6] ................................................................................. 9
Figure 1-6 靜電放電造成氧化層損傷................................................................................... 10
Figure 1-7 靜電放電測試200V ~ 1000V 材料融熔............................................................11
Figure 1-8 接觸窗突穿失效....................................................................................................11
Figure 2-1 三種靜電放電現象脈衝圖................................................................................... 14
Figure 2-2 人體靜電放電等效電路....................................................................................... 15
Figure 2-3 機械靜電放電等效電路....................................................................................... 16
Figure 2-4 元件充電測試等效電路....................................................................................... 17
Figure 2-5 X-Ray 掃瞄檢測影像........................................................................................... 18
Figure 2-6 光學顯微鏡進行高倍率觀察。........................................................................... 19
Figure 2-7 微光顯微鏡偵測失效位置影像[13]。.............................................................. 19
Figure 2-8 掃瞄式電子顯微鏡表面影像[14] ........................................................................ 20
Figure 3-1 I/O 端靜電放電元件放置[15].............................................................................. 22
Figure 3-2 (a) 二極體Diode電路圖及順偏及(b)逆偏I-V 特性。.................................. 23
Figure 3-3 二極體Diode Layout 設計參數......................................................................... 24
Figure 3-4 (a) 厚氧化層電晶體FOD電路圖及(b)雙極電晶體及操作模式[16] ................ 25
Figure 3-5 厚氧化層電晶體FOD layout 設計參數L 及DS .......................................... 25
Figure 3-6 (A) 閘極及源極接地又可稱為閘極接地N 型金氧半(GGNMOS) 電路圖及
(B)剖面圖................................................................................................................................ 26
Figure 3-7 閘極接地N 型金氧半(GGNMOS) 元件Layout 設計參數DS 及W...... 27
Figure 3-8 矽控整流SCR 電晶體剖面與連接方式........................................................... 28
Figure 3-9 矽控整流SCR Layout 設計參數....................................................................... 29
Figure 4-1 靜電放電元件設計窗口....................................................................................... 31
Figure 4-2 (A) ESD Implant 及(B) Silicide Block (RPO) 結構.......................................... 33
Figure 4-3 晶片針測黑箱及四個探針座的晶圓載台........................................................... 34
Figure 4-5 TLP 波形與驟回崩潰(Snapback effect) 特性電壓及電流關係曲線............... 37
Figure 4-6 實驗測試件元件的驟回特性電壓及電流關係曲線........................................... 39
Figure 5-1。(A) 閘極耦合觸發及(B) 基底耦合觸發........................................................ 42

表目錄
Table 1-1 環境中所產生的靜電放電能量............................................................................... 2
Table 1-2 IC產品之人體靜電放電能力分類........................................................................... 6
Table 1-3 IC產品之機器靜電放電能力分類........................................................................... 7
Table 1-4 顯示IC產品之元件放電能力分類[5]....................................................................... 7
Table 1-5 商業用半導體產品之抗靜電放電能力標準表....................................................... 8
Table 1-6 三種不同靜電放電特性所產生之峰值電流及上升至峰值的時間表[10]........... 12
Table 1-7 靜電放電造成失效表............................................................................................ 12
Table 4-1 實驗靜電放電元件測試件設計表......................................................................... 33
Table 4-2 傳輸線路脈衝量測驟回特性電壓及電流測試結果............................................. 39
[1] Tzong-Lin Wu “EMC Lab Material” page 9.
[2] A. Amerasekera, and C. Duvvury “ESD in Silicon Integrated Circuits” page
2.
[3] MIL-STD-883C method 3015.7 “ Military Standard Test Methods and Proc.
For Microelectronics ”, Dept. of Defense, Washington, D. C., U.S.A.,1989.
[4] EIA/JESD22-A115-A “EIA/JEDEC Standard” Electronic Industries
Association. 1997.
[5] JESD22-C101-A “JEDEC Standard” JEDEC Solid State Technology
Association, 2000)
[6] T. Green, "A review of EOS/ESD field failures in military equipment", in
proceedings of the 10th EOS/ESD symposium, pp. 7-14, 1988
[7] A. Amerasekera, and C. Duvvury “ESD in Silicon Integrated Circuits”
Chapter 8 page 237.
[8] A. Amerasekera, and C. Duvvury “ESD in Silicon Integrated Circuits”
Chapter 6 page 169.
[9] Mark Thomas and Carole LeClaire CSIC failure analysis group.
[10] S. Dabral, TT. Maloney, “Basic ESD and I/O Design”, Intel Corp.
Wiley, page 3,1998.
[11] H. Gieser, “Verfahren zur Charakterisierung von I ntegrierten
Schaltungen mit sehr schnellen Hochstromimpulsen (Methods for the
44
characterization of integrated circuits employing very high current
impulse)” in Dissertation Technische Universitaet Muenchen TUM,
Shaker-Verlag, Aachen, Germany, 1999.
[12] Yu-Chul Hwang “Electrostatic Discharge and Electrical Overstress
Failure of Non-Silicon Devices” University of Maryland page 67.
[13] Electrical Failure Analysis “Emission Microscope, EMMI” Material
Analysis Technology Company.
[14] Rafael Huerta “EDFAS 2008 Photo contest” National Semiconductor,
Santa Clara, California.
[15] A. Amerasekera, and C. Duvvury “ESD in Silicon Integrated Circuits”
page 121.
[16] Ben G. Streetman “Solid State Electronic Devices fourth edition” Page
238, 1995.
[17] Scott T Ward “Electrostatic Discharge Protection in CMOS” College of
Graduate Studies University of Idaho.
[18] Julio Guillermo Zoa, Gonzalo Andres Pacheco “TLP ESD models
correlation and approximation” Electronic Department-Faculty of
Engineering University of Euenos Aires, Argentina.
[19] T. J. Maloney and N. Khurana “Transmission Line Pulsing Techniques
for Circuit Modeling of ESD Phenomena” Intel Corporation.
[20] Ming-Dou Ker “ESD Protection in CMOS Intergrated Circuits” National
Chiao Tung University, Chapter 5.
45
[21] 葉宗立“適用於ESD 防護之島嶼型汲極MOS 電晶體” College of
Electrical Engineering and Computer Science, National Tsing Hua
University, page 39
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