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研究生:紀美伶
論文名稱:使用動態虛擬快取叢聚機制增進多核心系統之快取記憶體效能
論文名稱(外文):Enhancing Performance of Cache for Many-Core Systems Using Dynamic Virtual Cache Clustering
指導教授:張貴忠
口試委員:王益文陳德生
口試日期:2014-07-23
學位類別:碩士
校院名稱:逢甲大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:47
中文關鍵詞:多處理器晶片叢聚式快取記憶體晶片上網路
相關次數:
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  • 下載下載:6
  • 收藏至我的研究室書目清單書目收藏:0
多核心系統之快取記憶體是提供快速資料存取的重要角色。根據先前許多的論文研究結果,我們可以得知影響整個多核心系統最重要的元件就是最下層的快取記憶體。除此之外,多核心系統晶片需要大量共享晶片上的快取記憶體,藉此來增進不同核心之間資料存取的速度以及效能。為了解決傳統匯流排以及延遲問題的瓶頸,晶片網路被使用在非一致性快取架構(NUCA)上來達到同步記憶體的資料存取。
在多核心系統裡,不同的工作對於快取記憶體大小有不同的需求;在執行的過程中,每個工作對於快取記憶體空間的需求也是隨時都在變動。因此在本篇論文中,我們提出一個動態快取叢聚架構來分配適當的快取空間給不同的工作。分配的機制是根據執行過程中的記憶體存取需求來做考量。這個分配的機制稱為虛擬快取叢聚(Virtual Cache Clustering),可以動態調整各個工作的快取記憶體的叢聚大小。虛擬快取叢聚可以根據實際的記憶體空間需求來動態放大或縮小。此外,虛擬快取叢聚中的成員可以包含同一個實體叢聚中的快取記憶體或是跨不同叢聚的快取記憶體。根據實驗可知,我們提出的動態快取叢聚機制可以增加快取記憶體的使用率,減少快取失誤率並且改善資料的存取時間。
誌謝 i
摘要 ii
Abstract iii
Table of Contents iv
List of Figures vi
List of Tables viii
Chapter 1 Introduction 1
1.1 Motivation 2
1.2 Contributions 2
1.3 Thesis Organization 4
Chapter 2 Related Work 5
2.1 Many-core SoC 5
2.2 Network-On-Chip 5
2.3 NUCA 7
2.4 Cache Space Allocation Design 8
2.5 Comparisons 10
Chapter 3 Proposed Approach 11
3.1 Many-core Architecture with NUCA 11
3.2 Definition of Virtual Cache Cluster 12
3.3 Expansion and Contraction of Virtual Cache Cluster 13
3.4 Cache Policies in VCC 16
3.4.1 Data placement 16
3.4.2 Data Search 18
3.4.3 Replacement policy 19
Chapter 4 Experimental Results 21
4.1 Experiment environment 21
4.2 Experimental results 23
Chapter 5 Conclusion and Future Work 35
References 36
[1]Jeff Parkhurst, John Darringer, Bill Grundmann, “From Single Core to Multi-Core Preparing for a new exponential,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 67-72, November 2006.
[2]Eshel Haritan, Hiroyuki Yagi, Wayne Wolf, Toshihiro Hattori, Pierre Paulin, Achim Nohl, Drew Wingard, Mike Muller, “Multicore Design is the challenge! What is the solution? ,” Proceedings of the 45th annual Design Automation Conference, pp. 128-130, June 2008.
[3]Lei Chai, Qi Gao, Panda, D.K., “Understanding the Impact of Multi-Core Architecture in Cluster Computing: A Case Study with Intel Dual-Core System ,“ Proceedings of the Seventh IEEE International Symposium on Cluster Computing and the Grid, pp. 471-478, May 2007.
[4]Kuei-Chung Chang ,and Ting-Yin Kuo , “ Enhancing Performance of NUCA for Cluster-based Many-Core System Using Bank Loan Mechanism Assisted by Network-on-Chip ,” Master Thesis, Department of Information Engineering and Computer Science, Feng Chia University, 2012.
[5]Kuei-Chung Chang ,and Tzu-Yu Wen , “ Enhancing Performance of NUCA for Cluster-based Many-Core System by Cluster Filter,” Master Thesis, Department of Information Engineering and Computer Science, Feng Chia University, 2012.
[6]T.Trawick,“Multicore communication: today and the future,” Embedded Computing Design, March 2007.
[7]Baojun Qiao, Feng Shi, Weixing Ji, “A new Hierarchical Interconnection Network for Multi-core Processor,” Proceedings of the 2nd IEEE Conference on Industrial Electronics and Applications, pp. 246-250, May 2007.
[8]Jesshope CR, Miller PR, Yantchev JT, “High Performance Communications in Processor Networks, Computer Architecture,” Proceedings of the 16th Annual International Symposium on Computer Architecture, pp. 150-157, June 1989.
[9]Dietmar Tutsch and Gunter Hommel, “High Performance Low Cost Multicore NoC Architectures for Embedded Systems,” Proceedings of the International Workshop on Embedded Systems-Modeling, Technology and Applications, pp. 53-62, 2006.
[10]Partha Pratim Pande, Cristian Grecu, Michael Jones, Andre´ Ivanov, and Resve Saleh, “Performance Evaluation and Design Trade-Offs For Network-on-Chip Interconnect Architectures,” IEEE Transactions on Computers, Vol. 54, Issue 8, pp. 1025-1040, August 2005.
[11]Henrique C. Freitas and Philippe O. A. Navaux , “A high throughput multi cluster noc architecture,” Proceedings of the IEEE 11th International Conference on Computational Science and Engineering, pp. 56-63, July 2008.
[12]Lei Chai, Albert Hartono, Dhabaleswar K. Panda, “Designing High Performance and Scalable MPI Intra-node Communication Support for Clusters,” Proceedings of the IEEE International Conference on Cluster Computing, pp. 1-10, September 2006.
[13]Marek Tudruj, Lukasz Masko, “Dynamic SMP Clusters with Communication on the Fly in NoC Technology for Very Fine, Parallel and Distributed Computing,” Proceedings of the 3rd International Symposium on Parallel and Distributed Computing, pp. 97-104, July 2004.
[14]Changkyu Kim, Doug Burger, Stephen W. Keckler, “An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches,” Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, pp. 99-107, December 2003.
[15]Peter Deayton, Chung-Ping Chung, “Set Utilization Based Dynamic Shared Cache Partitioning,” IEEE 17th International Conference on Parallel and Distributed Systems, pp. 284-291,December 2011.
[16]Guang Suo, Xuejun Yang, Guanghui Liu, Junjie Wu, Kun Zeng, Baida Zhang and Yisong Lin, “IPC-based Cache Partitioning: An IPC-oriented Dynamic Shared Cache Partitioning Mechanism,” International Conference on Convergence and Hybrid Information Technology, pp.399-406, August 2008.
[17]Guang Suo, “Cache Partitioning on Chip Multi-processors for Balanced Parallel Scientific Applications,” International Conference on Parallel and Distributed Computing, Applications and Technologies, pp.124-129, December 2009.
[18]Sanchez, D., Kozyrakis, C. “Vantage: Scalable and Efficient Fine-Grain Cache Partitioning,” 38th Annual International Symposium, pp.57-68, June 2011.
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