本論文設計一個三階之三角積分調變器，並應用於語音系統中，信號頻寬約為20~24kHz，超取樣率(Oversampling ratio)為128，採樣速率(Sampling frequency)為6.144MHz，本文採用TSMC 1P6M 0.18μm標準製程，工作電壓為3.3V進行設計，先透過Matlab數學式的模擬來確認系統架構最高可以到達之規格，架構選擇前饋(Feedforward)系統架構，使的每一級積分器之輸出振幅相對較小，並且放寬放大器之架構或規格，以交換式電容電路(Switched capacitor)離散之方式來實現整體電路架構，最後信號雜訊失真比(Signal to noise plus distortion ratio: SNDR)最高可達到93.83dB之解析度，有效位元數(Effective number of bit: EOB)大約15bit，功率消耗率3.529mW，面積約為0.811x0.888 mm2。

The study topic of this paper is to design a sigma delta modulator for audio applications. TSMC 1P6M 0.18μm process is used to design the circuit with supply voltage 3.3V. System structure is based on the third order Feedforward(CIFF) and relax operation amplifier output swing. Oversampling ratio(OSR) is 128 and sampling frequency 6.144MHz. circuit implement with Switched capacitor circuit(discreet time). Max SNDR reach 93.83dB and EOB reach about 15bit. Power dissipations 3.529mW. Chip area is 0.811x0.888 mm2.

致謝 i
中文摘要 ii
Abstract iii
目錄 4
圖目錄 6
表目錄 8
第一章 緒論 9
1.1 發展現況 9
1.2 研究動機 9
1.3 論文概要 11
第二章 三角積分調變器原理 13
2.1 類比數位轉換器 13
2.2 效能指標 14
2.3 超取樣(Oversampling) 16
2.4 雜訊移頻(Noise shaping) 19
2.5 三角積分調變器架構 21
2.5.1 低階三角積分調變器(Low order SDM) 21
2.5.2 高階三角積分調變器(High order SDM) 23
2.5.3多位元量化(Multi-bit SDM) 24
2.5.4回授組態三角積分調變器(CIFB SDM) 24
2.5.5前饋組態三角積分調變器(CIFF SDM) 26
第三章 系統架構及規格分析 27
3.1 系統架構選擇考量 27
3.2Matlab數學模擬分析 28
3.3系統規格 28
3.4 系統規格模擬結果 29
第四章 電路設計及模擬 33
4.1 交換式電容積分器 33
4.1.1 電容之決定 33
4.1.2 類比開關之設計 34
4.2 運算放大器 37
4.3非重疊時脈產生器 44
4.4 偏壓電路 47
4.5 比較器(comparator) 49
4.6佈局量測考量 51
4.7 模擬結果 53
4.8量測考量 57
第五章 結論 58
5.1結果討論與比較 58
5.2 未來研究與討論 59
參考文獻 61

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