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研究生:劉昆燁
研究生(外文):Kun-Ye Liou
論文名稱:新穎式厚側壁介電層之複晶矽薄膜電晶體
論文名稱(外文):A Novel Poly-Si Thin Film Transistor with Thick-Spacer Dielectric on Source/Drain Area
指導教授:簡鳳佐簡鳳佐引用關係
指導教授(外文):Feng-Tso Chien
口試委員:邱顯欽陳啟文
口試委員(外文):Hsien-Chin ChiuChii-Wen Chen
口試日期:2014-07-21
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:50
中文關鍵詞:複晶矽薄膜電晶體元件不理想效應元件模擬軟體(ISE- TCAD)抬升式源汲極(RSD)熱載子效應
外文關鍵詞:poly-Si TFTsRaised Source/Drain (RSD)kink effectISE- TCAD
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專利申請中,暫不公開
致謝 ................................................................................. i
中文摘要 .........................................................................ii
英文摘要 ........................................................................ iv
目錄 ................................................................................ vi
圖目錄 ............................................................................ ix
表目錄 ............................................................................ xi
第一章 前言 ................................................................. 1
1-1 論文架構 ................................................................................ 1
1-2 薄膜電晶體(Thin Film Transistor,TFT)簡介及應用 .... 1
1-3 非晶矽薄膜電晶體(Amorphous-Silicon TFT) ..................... 2
1-4 複晶矽薄膜電晶體(Poly-Silicon TFT) ................................. 3
1-5 低溫複晶矽薄膜電晶體(LTPS-TFT)之關鍵製造技術 ....... 4
1-5.1 固相結晶 (Solid Phase Crystallization,SPC) .................... 5
1-5.2 金屬誘發結晶 (Metal-Induced Crystallization,MIC) ....... 6
1-5.3 準分子雷射退火 (Excimer Laser Annealing,ELA) .......... 7
1-6 複晶矽薄膜電晶體的不理想效應 ........................................ 8
1-6.1 漏電流效應(Leakage current effect) ..................................... 8
1-6.2 扭結效應(Kink effect) ......................................................... 10
1-6.3 熱載子效應(Hot carrier effect) ........................................... 12
1-7 複晶矽薄膜電晶體之常見結構 .......................................... 14
1-7.1 offset ..................................................................................... 14
1-7.2 Lightly Doped Drain (LDD) ................................................ 15
1-7.3 Raised Source/Drain(RSD) .................................................. 16
1-7.4 Gate Overlap Lightly Doped Drain (GOLDD) .................... 16
1-8 研究動機與方向 .................................................................. 17
第二章 文獻回顧與結構設計之動機 ........................ 18
2-1 歷史文獻回顧 ...................................................................... 18
2-1.1 Elevated Channel Thin Film Transistor ............................... 18
2-2 厚側壁介電層薄膜電晶體(TSD-TFT)之設計 ................... 19
第三章 TSD-TFT 之模擬分析與驗證 ....................... 21
3-1 前言 ...................................................................................... 21
3-2 TSD-TFT 結構模擬與分析 ................................................. 21
3-1.1 TSD-TFT 最佳製程參數之探討 ......................................... 21
3-2.2 TSD-TFT 之模擬驗證 ......................................................... 23
第四章 TSD-TFT 之實作結果討論 ........................... 29
4-1 前言 ...................................................................................... 29
4-2 實作製程步驟 ...................................................................... 29
4-3 電性參數之萃取 .................................................................. 34
4-3.1 臨界電壓(Threshold voltage, Vt ) ...................................... 34
4-3.2 次臨界擺幅(Subthreshold swing,S.S.) ............................. 35
4-3.3 導通與截止之電流比(On /Off current ratio) ...................... 36
4-3.4 載子遷移率(Mobility) ......................................................... 36
4-3.5 偏壓應力效應(bias stress effect) ......................................... 37
4-4 量測結果與討論 .................................................................. 37
4-4.1 TSD-TFT 之元件 SEM 圖 .................................................. 37
4-4.2 TSD-TFT 之轉換曲線圖與輸出曲線(Before H 2 anneal ) .. 39
4-4.3 TSD-TFT 之轉換曲線圖與輸出曲線(After H 2 anneal ) .... 40
4-4.4 偏壓應力效應的影響 .......................................................... 43
第五章 結論 ............................................................... 45
參考文獻 ....................................................................... 46
[1]S. D. Brotherton, “Topical review Polystalline silicon thin film transistors” Semicond. Sci. Technol., no. 10, pp. 721-738, 1995.
[2]B. Atwood, T. Ishii, T. Osabe, T. Mine, F. Murai and K. Yano, &;quot;SESO Memory: A CMOS compatible high density embedded memory technology for mobile applications&;quot;, Symp. VLSI Circuits Digest, pp 154-155, 2002.
[3]S. C. Chen , T. C. Chang , P. T. Liu , Y. C. Wu , P. S. Lin , B. H. Tseng , J. H. Shy , S. M. Sze , C. Y. Chang and C. H. Lien &;quot;A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory&;quot;, IEEE Electron Device Lett., vol. 28, no. 9, pp.809 -811 2007
[4]K. Werner &;quot;The flowering of flat displays&;quot;, IEEE Spectr., vol. 34, no. 5, pp.40 -49 1997
[5]G. Ottaviani , D. Sigurd , V. Marrello , J. W. Mayer and J. O. McCaldin “Crystallization of Ge and Si in metal films,” Jour. Appl. Phys., vol. 45, no. 4, 1974
[6]T. J. Konno and R. Sinclair, “Metal-contact induced crystallization of semiconductors,” Materials Science Engineering, vol. A179-180, 1994.
[7]L. Hultman , A. Robertsson , H. T. G. Hentzell , I. Engstrom and P. A. Psaras &;quot;Crystallization of amorphous silicon during thin-film gold reaction&;quot;, J. Appl. Phys., vol. 62, no. 9, pp.3647 -3655 1987
[8]S. F. Gong, H. T. G. Hentzell, A. E. Robertsson, L. Hultman, S.‐E. Hörnström and G. Radnoczi “Al-doped and Sb-doped polycrystalline silicon obtained by means of metal-induced crystallization” Journal of Applied Physics, vol. 62, No. 9, pp. 3726-3732 Nov. 1987.
[9]G. Radnoczi , A. Robertsson , H. T. G. Hentzell , S. F. Gong and M.-A. Hasan &;quot;Al induced crystallization of a-Si&;quot;, J. Appl. Phys., vol. 69, no. 9, pp.6394 -6399 1991
[10]R. J. Nemanich , C. C. Tsai , M. J. Thompson and T. W. Sigmon &;quot;Interference enhanced Raman scattering study of the interfacial reaction of Pd on a-Si: H&;quot;, J. Vac. Sci. Technol., vol. 19, pp.685 -688 1981
[11]G. Liu and S. Fonash, &;quot;Selective area crystallization of amorphous silicon films by low-temperature rapid thermal annealing,&;quot; Appl. Phys Lett., vol. 55, no. 7, pp. 660-662, Aug. 1989.
[12]J.G. Fossum , A. Ortiz-Conde , H. Shichijo and S. K. Banerjee &;quot;Anomalous leakage current in LPCVD polysilicon MOSFET&;#39;s&;quot;, IEEE Trans. Electron Devices, vol. ED-32, pp.1878 -1884 1985
[13]K. R. Olasupo and M. K. Hatalis &;quot;Leakage current mechanism in submicron polysilicon thin-film transistors&;quot;, IEEE Trans. Electron Devices, vol. 43, no. 8, pp.1218 -1223 1996
[14]M. Hack, I.-W. Wu, T. J. King, and A. G. Lewis, &;quot;Analysis of leakage currents in poly-silicon thin film transistors&;quot;, IEDM Tech. Dig., pp.385 -388 1993
[15]D. De Venuto, M.J. Ohletz, “Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits,” Microelectronics Journal, Vol.34 pp.889-895, 2003

[16]S. Bindra, S. Haldar and R.S. Gupta, “Modeling of kink effect in polysilicon thin film transistor using charge sheet approach,” Solid-State Electronics, Vol.47, pp.645-651, 2003.
[17]E.Takeda &;quot;Hot-carrier effects in submicrometer MOS VLSIs&;quot;, Proc. Inst. Elect. Eng. I—Solid-State Electron Devices, vol. 131, no. 5, pp.153 -162 1984
[18]E. Takeda , N. Suzuki and T. Hagiwara &;quot;Device performance degradation to hot-carrier injection at energies below the Si-SiO2 energy barrier&;quot;, Proc. IEEE Int. Electron Dev. Meeting, vol. 29, pp.396 -399 1983
[19]A. J. Walker , S. Nallamothu , E. H. Chen , M. Mahajani , S. B. Herner , M. Clark , J. M. Cleeves , S. V. Dunton , V. L. Eckert , J. Gu , S. Hu , J. Knall , M. Konevecki , C. Petti , S. Radigan , U. Raghuram , J. Vienna and M. A. Vyvoda &;quot;3D TFT-SONOS memory cell for ultra-high density file storage applications&;quot;, VLSI Symp. Tech. Dig., pp.29 -30 2003
[20]T. Shimoda, H. Ohsima, S. Miyashita, M. Kimura, T. Ozawa, I. Yudasaka, S. Kanbe, H. Kobayashi, R. H. Friend, J. H. Burroughes, and C. R. Towns, &;quot;High resolution light emitting polymer display driven by low temperature polysilicon thin film transistor with integrated driver&;quot;, Proc. Asia Display, pp.271 1998
[21]A. G. Lewis , I.W. Wu , T.Y. Huang , A. Chiang and R.H. Bruce &;quot;Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs&;quot;, IEDM Tech. Dig., pp.843 -846 1990
[22]H. Ohshima and S. Morozumi &;quot;Future trends for TFT integrated circuits on glass substrates&;quot;, IEDM Tech. Dig., pp.157 -160 1989
[23]X. Duan , Y. Huang , and C. M. Lieber , “Nonvolatile memory and programmable logic from molecule-gated nanowires,” Nano Lett., vol. 2, no. 5, pp. 487–490, 2002.
[24]Y. Cui, Q. Wei, H. Park, C. M. Lieber, “Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species,” Science, vol. 293, pp. 1289–1292, 2001.
[25]Z. Li , Y. Chen ,X. Li , T. I. Kamins , K. Nauka , and R. S. Williams, “Sequence- specific label-free DNA sensors based on silicon nanowires,” Nano Lett., vol. 4, pp. 245–247, 2004
[26]A. Kumar and J. K. O. Sin &;quot;Influence of lateral electric field on the anomalous leakage current in polysilicon TFTs&;quot;, IEEE Electron Device Lett., vol. 20, no. 1, pp.27 -29 1999
[27]K. P. Anish Kumar , J. K. O. Sin , C. T. Nguyen and P. K. Ko &;quot;Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors&;quot;, IEEE Trans. Electron Devices, vol. 45, no. 12, pp.2514 -2520 1998
[28]陳志強 編著 “LTPS低溫複晶矽顯示器技術” 全華科技圖書股份有限公司 p.2-05~2-07 2004
[29]N.I. Lee , J.W. Lee , H.S. Kim and C.H. Han , “High-Performance EEPROM’s Using N- and P-Channel Polysilicon Thin-Film Transistors with Electron Cyclotron Resonance N O-Plasma Oxide,” IEEE Electron Device Lett., vol. 20, no. 1, pp.15 -17 1999
[30]J.H. Oh , H.J. Chung , N.I. Lee and C.H. Han &;quot;A high-endurence low-temperature polysilicon thin-film transistor EEPROM cell&;quot;, IEEE Electron Device Lett., vol. 21, no. 6, pp.304 -306 2000
[31]B.A. Khan and R. Pandya &;quot;Activation-energy of source-drain current in hydrogenated and unhydrogenated polysilicon thin-films transistors&;quot;, IEEE Trans. Electron Devices, vol. 37, pp.1727 -1734 1990
[32]J. D. Bernstein, S. Qin, C. Chan, and T. J. King, &;quot;Hydrogenation of polycrystalline silicon thin film transistors by plasma ion implantation&;quot;, IEEE Electron Device Lett., vol. 16, pp.421 -423 1995
[33]S.W. Tsao , T.C. Chang , S.Y. Huang , M.C. Chen , S.C. Chen , C.T. Tsai,Y.J. Kuo,Y.C. Chen,W.C. Wu, “Hydrogen-induced improvements in electrical characteristics of a-IGZO thin-film transistors,” Solid-State Electronics, vol. 54, no. 12,pp. 1497–1499, Dec. 2010
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