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研究生:趙俞勛
研究生(外文):Shu-Syun Jhao
論文名稱:具高量測範圍與高電壓變異容忍度之全數位晶片內延遲量測電路設計
論文名稱(外文):Wide Measurement Range and High Supply Voltage Variation Tolerance All-Digital On-Chip Delay Measurement Circuit Design
指導教授:盛鐸
指導教授(外文):Duo Sheng
口試委員:林寬仁黃執中盛鐸
口試委員(外文):Kuan-Jen LinChih-Chung HuangDuo Sheng
口試日期:2014-06-25
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電機工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:63
中文關鍵詞:延遲量測電路設計
外文關鍵詞:Delay Measurement Circuit Design
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在本篇論文中,具高量測範圍與高電壓變異容忍度之全數位晶片內延遲量測電路設計中被提出。所提出的晶片內延遲量測電路不僅不需要任何額外的自我偏壓或校正電路即可對電壓變異擁有高抵抗能力而且亦具有高量測範圍。
所提出的晶片內延遲量測電路被實現在TSMC 0.18μm 標準CMOS 製程中,從模擬結果顯示其延遲量測範圍可達1.2ns。因為利用了低電壓敏感度游標尺式量測架構之延遲線以及雙全數位延遲鎖定迴路,且此游標尺延遲線隨著 + 10% 的供應電壓變異,延遲變異量約為1%,所以達到整體電路量測解析度約為20.388ps。本篇所提出的晶片內延遲量測電路使用全數位設計的方式來實現,因此它們皆非常適合於系統晶片的應用以及易整合於系統中。

In this thesis, wide measurement range and high supply voltage variation Tolerance all-digital on-chip delay measurement (OCDM) circuit design are proposed. The OCDM circuits not only have a high immunity to supply voltage variations without extra self-biasing or calibration circuit, but also achieve high wide measurement range.
The proposed OCDM circuit is implemented in TSMC 0.18μm standard CMOS technology, and simulation results show that measurement range can be improved to 1.2ns. Because using the vernier delay line with low supply sensitivity and two all-digital delay-locked loops, also the vernier delay line’s delay variation is about 1% with + 10% supply voltage variation. Also, the measurement resolution of this circuit is about 20.388ps with + 10% supply voltage variation.The proposed OCDM circuits can be implemented in all-digital design manner, making it very suitable for SOC application as well as system-level integration.

摘要……………………………………………………………….……………… i
英文摘要………………………………………………………………………… ii
誌謝……...………………………………………………………………………… iii
表目錄…………………………………………………………………………… vi
圖目錄…………………………………………………………………………… vii
第一章 緒論 1
1.1 研究動機 1
1.2 晶片內延遲量測電路架構概要 5
1.3 論文架構 9
第二章 全數位延遲鎖定迴路設計探討 10
2.1 延遲鎖定迴路架構概要 10
2.2 全數位延遲鎖定迴路架構概要 11
2.3 設計全數位延遲鎖定迴路的考量 13
2.4 所提出之數位延遲鎖定迴路 16
2.5 寬範圍的晶片內延遲量測電路架構 17
第三章 具低電壓敏感度的游標尺式延遲量測架構概要 23
3.1 游標尺式延遲量測架構概要 23
3.2 具低電壓敏感度的游標尺式延遲線概要 24
3.3 總結 31
第四章 晶片內延遲量測電路設計 32
4.1 可調式延遲元件架構設計[12] 32
4.2 具低電壓敏感度游標尺式延遲線運用 36
4.3 晶片內數位延遲鎖定迴路和游標尺式延遲線量測架構的關係 38
4.4 相位頻率偵測器[10] 44
4.5 前置輸入電路架構 46
4.6 總結 49
第五章 實驗結果 50
5.1 模擬結果 50
5.1.1 延遲鎖定迴路模擬結果 51
5.1.2 前置輸入電路模擬結果 53
5.1.3 游標尺式量測電路模擬結果 55
5.2 晶片量測方法 58
5.3 總結 60
第六章 結論與未來展望 61
參考文獻……………………………………………………………...……………62

[1]Abhishek Jain, Andrea Veggeti, Dennis Crippa and Pierluigi Rolandi, “On-chip delay measurement circuit,” Proc. 17th IEEE European Test Symposium (ETS), pp. 1-6, May 2012.
[2]Masahiro Sasaki, Nguyen Ngoc Mai Khanh and Kunihiro Asada, “A circuit for on-chip skew adjustment with jitter and setup time measurement,” Proc. IEEE Asian Solid State Circuits Conference (A-SSCC), pp. 1-4, Nov. 2010.
[3]Songwei Pei, Huawei Li and Xiaowei Li, “A high-precision on-chip path delay measurement architecture,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 9, pp. 1565-1577, 2012.
[4]Ming-Chien Tsai, Ching-Hwa Cheng and Chiou-Mao Yang, “An all-digital high-precision built-in delay time measurement circuit,” Proc. 26th IEEE VLSI Test Symposium, pp. 249-254, 2008.
[5]Ching-Che Chung and Wei-Jung Chu, “An all-digital on-chip jitter measurement circuit in 65nm CMOS technology,” Proc. International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), pp. 1-4, Apr. 2011.
[6]Xiaoxiao Wang, Mohammad Tehranipoor and Ramyanshu Datta, “Path-RO: a novel on-chip critical path delay measurement under process variations,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 640-646, Nov. 2008.
[7]Xiaoxiao Wang, Mohammad Tehranipoor, SeniorSaji George, Dat Tran and LeRoy Winemberg, “Design and analysis of a delay sensor applicable to process/environmental variations and aging measurements,” IEEE Transactions Very Large Scale Integration (VLSI) System, vol. 20, no. 8, pp. 1405-1418, Aug. 2012.
[8]S. Schidl, K. Schweiger, W. Gaberl and H. Zimmermann, “Analogously tunable delay line for on-chip measurements with subpicosecond resolution in 90 nm CMOS,” Electron. Lett., vol. 48, no. 15, pp. 910-911, 2012.
[9]Duo Sheng and Hsiu-Fan Lai, “High delay resolution and high supply voltage variation tolerance all-digital on-chip delay measurement circuit design,” M.S. Thesis, Department of Electrical Engineering Fu Jen Catholic University, Taipei, Taiwan, 2014.
[10]Chen-Yi Lee and Ching-Che Chung, “Automatic Synthesis of Timing-Locked Loops for SoC Designs,” Ph.D. Thesis, College of Electrical Engineering and Computer Science National Chiao Tung Unversity, Hsinchu, Taiwan, 2013.
[11]劉深淵、楊清淵,鎖相迴路,滄海書局,100年1月。
[12]Duo Sheng, C.-C. Chung and C.-Y. Lee, “Fast-lock all-digital DLL and digitally controlled phase shifter for DDR controller applications,” IEICE Electronics Express, vol. 7, no. 9, pp. 634-639, May 2010.
[13]D.-C. Lee, K.-Y. Kim, Y.-J. Min, K.-M. Kim, A. Abdullah, J. Park and S.-W. Kim, “A low-power all-digital PLL with power optimized digitally controlled oscillator,” Proc. IEEE Int. Conf. on Electron Devices and Solid-State Circuits, pp. 1-4, 2010.
[14]Duo Sheng, Ching-Che Chung, Hsiu-Fan Lai and Shu-Syun Jhao, “High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications,” IEICE Electronics Express, vol. 11, no. 3, pp. 1-6, Jan. 2014.

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