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研究生:陳柏愷
研究生(外文):Po-Kai Chen
論文名稱:28奈米高介電質製程在PDA或DPN氮化 處理下以探討pMOSFETs元件之爾利效應
論文名稱(外文):Early Effect Exposing Performance of 28nm HK/MG pMOSFETs under PDA or DPN Nitridation Treatment
指導教授:徐 璠王 木 俊
指導教授(外文):Fang HsuMu-Chun Wang
口試委員:王錫九
口試委員(外文):Shea-Jue Wang
口試日期:2014-06-26
學位類別:碩士
校院名稱:明新科技大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:84
中文關鍵詞:Early效應閘極氧化層去耦合電漿氮化製程後退火氮化製程高介電係數材料
外文關鍵詞:Early effectgate oxideDPNPDAhigh-K
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隨著科技的進步,半導體製程技術中的金氧半場效電晶體已從次微米的世代進入到28奈米或者更小的世代,並且按照摩爾定律(Moore’s law)的原則下前進,元件尺寸的微縮除了是要將成本降低以及增加積體電路中元件的密度之外,其中最主要的還是提升元件的操作速度。而在進入32奈米時,有些半導體大廠選擇高介電係數材料(High-K)來取代傳統製作閘極氧化層時,使用的二氧化矽或氮氧化矽材料,使其增加閘極電容值,以提升MOSFET元件的效能。另外,高介電係數材料容易受溫度的變化影響,無法承受溫度過高的高溫製程,在高溫狀態下容易有結晶化的情形發生。在目前的先進製程中,非晶化的閘極氧化層較不容易漏電,比較符合元件性能的需求。
High-K材料雖然有其優點,但是也容易產生氧空缺,使得電晶體的臨界電壓(VT)不易受控制,閘極介電層的品質也較易劣化,並使閘極介電層和電晶體的通道表面鍵結不良等諸多不利因素。因此,假設我們能在High-K材料沉積後,以些許的氮化以填補此空缺,其上述缺點則有機會能被改善。在此提出兩種可行的製程方式:去耦合電漿氮化(DPN)以及沉積後高溫退火氮化(PDA)。
本論文以28奈米製程元件為基礎,閘極介電層的部分,則選擇高介電係數介電層,採用氧化鉿及氧化鋯作為材料,並配合上述的兩種不同氮化製程方式,以爾利(Early)效應來探討HK/MG pMOSFETs 元件的驅動電流變化等電性特性,並比較在不同的氮濃度與退火溫度下的輸出特性曲線。並提出一個可行性的元件模型,以修正早期部分的元件電特性模型,提升IC設計者之設計空間(Design window)自由度。

With the advancement of technology, the feature size of field-effect transistors coming from semiconductor manufacturing process technology has evolved from sub-micron to 28nm process generation or beyond. Following the Moore’s law, besides the reduction of process cost and the increase of device density in IC due to the dimensional shrinkage of transistor devices, the increase of transistor switch speed is chiefly considered. Promoting until 32-nm node, some semiconductor companies applied the high-K material replacing the SiO2 as gate dielectric. But, the characteristics of high-K material are influenced easily by deposited temperature, especially at the high temperature status. In other words, the crystallization effect for pure high-K material will be obviously observed at the high temperature and easily cause higher gate leakage. Therefore, the amorphous gate dielectric in the advanced process is more impressive due to the device concern.
Although high-K materials propose several benefits, there is oxygen vacancy to difficultly control the threshold voltage (VT) of a transistor and easily degrade the integrity of gate dielectric. The quality of interface state between gate dielectric and channel surface is a latent issue. Therefore, if these drawbacks using some nitridation process to repair the vacancy after high-K deposition is acceptable. There are two feasible nitridation processes: decoupled-plasma nitridation (DPN) and post deposition annealing (PDA).
In this project, gate high-k material used to 28nm devices for basis and gate dielectric with a profile of HfOx/ZrOy/HfOz (HZH) was deposited. Then, the decoupled plasma nitridation (DPN) process or post deposition annealing (PDA) was employed to HZH annealing. The annealing temperature and the nitrogen concentration contributed to electrical characteristics of HK/MG pMOSFETs probed by Early effect was investigated. Through this study, some of device models compared with the traditional must be modified to increase the design window for IC designers.

目 錄

摘 要 I
Abstract II
誌謝 IV
目 錄 VI
表目錄 IX
圖目錄 X
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
第二章 元件物理基礎及特性 4
2.1 能帶架構 4
2.2 載子的傳輸方式 6
2.3 載子散射機制 7
2.4 P-N接面 10
2.5 MOSFET 元件結構與特性 11
2.5.1 平帶狀態(Flat-band condition) 12
2.5.2 聚集效應(Accumulation) 13
2.5.3 空乏效應(Depletion) 14
2.5.4 反轉效應(Inversion) 15
2.6 MOSFET元件基本輸出特性曲線 16
2.6.1截止區(Cutoff region) 17
2.6.2線性區(Linear region) 17
2.6.3飽和區(Saturation region) 18
2.7 MOSFET元件基本轉移特性曲線 19
2.8 MOSFET 元件其他特性與參數 21
2.8.1 遷移率退化(Mobility degradation) 21
2.8.2 次臨界特性(Subthreshold characteristics) 22
2.8.3 臨界電壓的控制(VT adjustment) 23
2.8.4 基板偏壓效應(Body effect) 24
2.9 MOSFET元件短通道效應 25
2.9.1 通道長度調變(Channel length modulation, CLM) 26
2.9.2 載子速度飽和(Velocity saturation) 27
2.9.3 臨界電壓的下滑 28
2.9.4 汲極引發的能障下降 29
2.9.5 貫穿效應 30
第三章 新世代High-K材料製程 32
3.1 High-K 介電質特性 32
3.1.1 Band offset與介電常數 34
3.1.2 High-K 介電質熱穩定性 36
3.1.3 High-K 介電質結晶化 36
3.1.4 界面品質 37
3.2 High-K 介電質電性特性 38
3.2.1 ZrO2介電質 38
3.2.2 HfO2介電質 39
3.2.3 HfLaO介電質 40
3.2.4 HfAlO介電質 41
3.3 High-K 介電質相容性整合 42
3.3.1 閘極相容性 42
3.3.2 可靠度問題 44
3.3.3 介電層沉積方式 46
3.3.4 High-K 介電質閘極製程 47
第四章實驗結果 49
4.1 實驗架構說明 49
4.2 半導體量測平台介紹 50
4.3 測試元件介紹 51
4.4 實驗條件 52
4.5 實驗結果 54
4.5.1 第一階段實驗結果 54
4.5.2 第二階段實驗結果 65
4.5.3 第三階段實驗結果 71
第五章 結論 78
參考文獻 79
作者簡介 84

參考文獻

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