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研究生:黃韋超
研究生(外文):Wei-Chao Huang
論文名稱:應用於 IEEE 802.11ad 之全數位頻率合成器
論文名稱(外文):All Digital Frequency Synthesizer For IEEE 802.11ad
指導教授:楊清淵楊清淵引用關係
指導教授(外文):Ching-Yuan Yang
口試委員:陳超群
口試委員(外文):Chao-Chun Chen
口試日期:2014-07-03
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:88
中文關鍵詞:
外文關鍵詞:no
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由於在寬頻與高傳輸率的訴求之下,高頻通訊技術是最基礎也是無可或缺的一環,而為了使無線通信系統的本地振盪信號和數位系統的時脈信號產生穩定信號,鎖相迴路已經成為一個重要且普遍的技術。本篇論文實作可應用於 IEEE802.11ad 通訊協定的全數位頻率合成器,希望藉由數位電路對於製程、電壓和溫度變異具有高抗敏感度的特性,來實現電路。

論文實現了兩個全數位頻率合成器,第一個架構利用兩種不同解析度的時間數位轉換器,希望藉由較大解析度的迴路來加快鎖定速度,而較高解析度的迴路換取更好的抖動表現,其製程是使用台積電 90 奈米製程,晶片面積為978.896um*995.72um,迴路的相位雜訊為-93.7 dBc/Hz@1MHz,在 1.2V 的操作電壓下,消耗功率為 53mW,鎖定時間為 5us。第二個架構則是利用兩組不同解析度的時間數位轉換器配合具有兩個解析度的數位控制振盪器,以獲得更快的鎖定時間和更高的解析度,製作上同樣使用台積電 90 奈米製程,晶片面積為923.79um*978.905um,迴路的相位雜訊為-102.93 dBc/Hz@1MHz,在 1.2V 的操作電壓下,消耗功率為 71.2mW。

Because of the demands of broadband and high transmission rate , high -frequency communication technology is the most basic and indispensable part. To generate stable local oscillator signal for wireless communication systems and stable clock signal for digital systems , phase-locked loop has become an important and popular technology. This thesis implements all-digital frequency synthesizers can be applied to the protocol of IEEE 802.11ad. The superiority of a digitalized PLL can have a higher tolerance to against the process , voltage and temperature variations than an analog PLL to achieve our goals.

This thesis mainly discribes in two circuits, the first one circuit uses two different resolution of digital converters. It can be separated into two loops , one of two loops which has lager resolution attempting to accelerate the locked speed and the other loop with small resolution is for higher jitter performance. It is fabricated in TSMC 90nm CMOS process. The phase noise of the all digital frequency synthesizer is -93.7 dBc/Hz@1MHz.The locking time is 5us and the power dissipation is 75mW under 1.2V supply voltage. The chip size is 978.896um*995.72um.

The second topology uses two different resolution of digital converters and combined with a digitally controlled oscillator has two resolutions to shorten the locking time and enhance the jitter performance. The phase noise of the all digital frequency synthesizer is -102.93 dBc/Hz@1MHz.The locking time is 1.5us and the power dissipation is 71.2mW under 1.2V supply voltage. The chip size is 923.79um*978.905um.

誌謝.................I
摘要.................II
Abstract v III
目次.................IV
表目次.................VII
圖目次.................VIII
第一章 緒論.................1
1.1 研究動機.................1
1.2 全數位頻率合成器的優點.................3
1.3 論文架構.................3
第二章 全數位鎖相迴路.................4
2.1 類比式鎖相迴路.................4
2.1.1 頻率合成器.................4
2.1.2 整數型頻率合成器.................5
2.1.3 非整數型頻率合成器.................6
2.2 全數位鎖相迴路.................6
2.2.1全數位鎖相迴路簡介.................7
2.2.2相位數位轉換器.................7
2.2.3數位迴路濾波器.................8
2.2.4時間數位轉換器.................9
2.2.5數位三角積分調變器.................9
2.2.6數位碼控制壓控振盪器.................10
2.3 建立全數位鎖相迴路模型.................11
2.3.1相位數位轉換器的模型.................11
2.3.2一階數位迴路濾波器的模型.................12
2.3.3一階三角積分調變器的模型.................14
2.3.4數位碼壓控振盪器的模型.................14
2.3.5全數位鎖相迴路模型.................15
2.4 迴路參數的模擬.................15
2.4.1全數位鎖相迴路 S-domain 線性模型.................16
2.4.2二階充電泵鎖相迴路的分析.................18
2.4.3二階全數位鎖相迴路的分析.................19
2.5 全數位鎖相迴路的雜訊分析.................21
2.5.1全數位鎖相迴路的雜訊源.................21
2.5.2雜訊特性推導.................22
2.5.3時間數位轉換器的雜訊.................24
2.5.4數位控制振盪器的雜訊.................25
2.5.5整個迴路的雜訊.................27
第三章數位壓控振盪器.................29
3.1壓控振盪器基本介紹.................29
3.1.1壓控振盪器操作原理.................29
3.1.2振盪器共振腔.................31
3.1.3相位雜訊.................32
3.2 數位控制振盪器.................34
3.2.1電路模擬.................35
3.2.2晶片量測.................36
3.3 結論.................38
第四章 應用於 802.11ad 全數位鎖相迴路研究.................39
4.1 研究計畫之背景及目的.................39
4.1.1 研究背景.................39
4.1.2 規格選定.................40
4.1.3 電路架構.................41
4.2 內部電路介紹.................43
4.2.1 相位頻率偵測器.................44
4.2.2 相位選擇器.................44
4.2.3 時間數位轉換器.................45
4.3.4 粗調時間數位轉換器.................45
4.3.5 數位控制振盪器.................46
4.3.6 注入鎖定倍頻器.................46
4.3.7 除頻器.................47
4.3 系統分析.................50
4.3.1 快速鎖定迴路分析.................50
4.3.2 高解析迴路分析.................54
4.4 電路模擬結果.................58
4.5 量測結果.................61
4.5.1 量測考量.................61
4.5.2 量測結果.................63
第五章 應用於 802.11ad 雙迴路快速鎖定全數位鎖相迴路研究.................66
5.1 研究之目的.................66
5.1.1 電路架構.................66
5.1.2 遊標尺時間數位轉換器.................67
5.1.3 雙解析度數位控振盪器.................68
5.2 系統分析.................70
5.2.1 鎖頻迴路分析.................70
5.2.2 鎖相迴路分析.................74
5.3模擬結果................. 78
5.4量測結果.................80
第六章 結論.................84
參考文獻.................85


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