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研究生:李良哲
研究生(外文):Liang-CheLi
論文名稱:三維電路之堆疊前測試、堆疊後測試及矽穿孔測試架構及方法
論文名稱(外文):On-Chip 3D-IC Test System Design for Pre-bond, Post-bond, TSV Test and TSV Diagnosis Based on IEEE 1838 Standard
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:53
中文關鍵詞:測試平台三維電路測試流程三維電路測試架構
外文關鍵詞:Test Platform3D-IC Test Flow3D-IC DfT
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三維晶片利用晶片內部的矽穿孔技術減少晶片內電路彼此間接線長度與提升輸出入端頻寬限制,並有利於在不同製程世代下完成之記憶體、邏輯與類比電路進行異質整合,然而由於一顆三維晶片是由許多不同晶粒所堆疊成,因此在測試流程上較二維晶片更為複雜,在目前對三維晶片的測試流程可分為堆疊前和堆疊後測試,其中堆疊後測試包含部分堆疊、矽穿孔和完整堆疊測試。本篇論文係提出低成本、高品質之測試機制,乃於包裹測試標準測試介面IEEE std. 1838之三維晶片加入所設計之三維測試平台,使整體為一個三維測試系統,此測試系統在測試時只需透過較低價位的測試機台或電腦透過1149.1的訊號線傳送所需之測試向量和測試資料至測試平台,三維測試平台能即可產生控制訊號並於平台內部完成三維晶片測試所需之測試流程,達到三維電路的堆疊前和堆疊後測試,藉由此三維測試系統可大幅減少對外部測試機台之需求,進而降低三維晶片的測試成本,進一步的提出一有效率的矽穿孔測試架構,此架構能在不增加整體測試時間下並多次測試矽穿孔,進而提高矽穿孔良率。此外,我們亦設計一圖形介面軟體模組,協助測試者 協助測試者 協助測試者 協助測試者 協助測試者 快速整合電路於三維測試系統並控制三維測試平台的測試流程之功能 測試流程之功能 測試流程之功能 測試流程之功能 測試流程之功能 測試流程之功能 測試流程之功能 。在實驗的結果顯示,我們僅須1149.1的訊號線傳送測試資料至平台即可執行堆疊前之三維晶片底層的邏輯電路測試,堆疊後邏輯電路測試、記憶體測試和類比電路測試,以及堆疊後的矽穿孔測試和診斷,並能在不增加測試時間下對單一矽穿孔達到數十至數萬的測試次數。
3D-IC uses the Through Silicon Via (TSV) technology to reduce the connection length between each other circuits and enhance I/O bandwidth. It is also suitable to heterogeneous integration for memory, logic and analog circuits. However, due to the stacked structure with many different dies, the 3D-IC test flow is more complex than the 2D-IC. In the current research on test flow of 3D-IC, it can be divided into two main steps, Pre-bond and Post-bond test. The Post-bond test contains the partial stack, TSV and complete stack test. A low-cost and high-quality test mechanism is proposed in this thesis. We integrate the 3D-IC Test Platform to 3D-IC wrapped with the test interface called IEEE std. 1838, and the overall circuits become a 3D-IC Test System. The system just needs the external equipment or computer through 1149.1 signals sends the required test vectors and test data to platform and then it will generate all control signals and finish the 3D-IC test flow to achieve Pre-bond and Post-bond test and diagnosis for 3D-IC. It can significantly reduce the demand for external test equipment and reduce the test cost of 3D-IC chips by this 3D-IC Test System. In order to improve the yield of TSV by N-detection method, we further propose an efficient test framework of TSV under the overall test time no increasing; In addition, we design a graphical user interface (GUI) to help testers to integrate circuits with 3D-IC Test System quickly and controls the test flow of 3D-IC Test Platform. In experimental results, we just use 1149.1 signals to send the test data to platform and then the platform can effectively execute test functions that contain bottom die logic circuit test in Pre-bond test, logic circuit, memory and analog circuit test in Post-bond test, as well as TSV test and diagnosis. Otherwise the platform can test a single TSV tens to tens of thousands times without increasing test time.
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 RELATED WORK & BACKGROUND 4
2.1. RELATED WORK 4
2.1.1. On-chip Test [7] 4
2.1.2. 3D-IC DFT Architecture [8-10] 5
2.1.3. TSV Test and Diagnosis [11-15] 9
2.2. BACKGROUND 11
2.2.1. IEEE Standard 1838 11
2.2.2. Maximum Aggressor Fault Model 14
CHAPTER 3 OVERVIEW OF THE ON-CHIP TEST 3D-IC TEST SYSTEM 16
3.1. OVERVIEW OF THE 3D-IC TEST SYSTEM 16
3.2. FEATURES OF THE ON-CHIP 3D-IC TEST PLATFORM 19
3.3. TEST FLOW OF THE ON-CHIP 3D-IC TEST SYSTEM 20
CHAPTER 4 IMPLEMENTATION OF THE 3D-IC TEST PLATFORM 22
4.1. OVERALL ARCHITECTURE OF TAM CONTROLLER 22
4.2. TEST PROCEDURES OF EACH TEST MODE FOR TAM CONTROLLER 25
4.2.1. Pre-bond Test Mode & Post-bond Test Mode 25
4.2.2. Memory BIST Mode & ADC BIST Mode in Post-bond 26
4.2.3. TSV Test & Diagnosis Mode 26
4.3. DESIGNS FOR MEMORY BIST 27
4.4. DESIGNS FOR TAM CONTROLLER 28
4.4.1. JTAG Unit 28
4.4.2. Decoder Unit 29
4.4.3. Setup Unit 30
4.4.4. 1838 Control Signal Generator Unit 31
4.4.5. Shift Buffer Unit 33
4.4.6. Comparator Unit 34
4.4.7. Mask & Golden Generator Unit 35
CHAPTER 5 EXPERIMENTAL RESULTS 37
5.1. EXPERIMENTAL ENVIRONMENT 37
5.2. SIMULATION RESULTS 39
5.3. ANALYZING THE AREA OVERHEAD 42
5.4. CALCULATE THE TEST TIMES OF TSV 45
5.5. CALCULATE OF TEST CYCLES REDUCTION 48
CHAPTER 6 CONCLUSIONS 49
CHAPTER 7 FUTURE WORK 50
REFERENCES 51

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